AME9002 Datasheet, PDF (12/37 Pages) Asahi Kasei Microsystems – CCFL Backlight Controller

AME, Inc.
AME9002
Preliminary
CCFL Backlight Controller
stantly (i.e. a duty cycle of 100%), although the power
would be unregulated in this case.
Figures 6,7 illustrates various oscilloscope waveforms
generated by the CCFL circuit in operation. These fig-
ures show that the duty cycle of the gate drive at Q2
decreases as the battery voltage increases from 9 V to
21 V (as one would expect in order to maintain the same
output power).
The first three traces in Figures 6 and 7 show the gate
drive waveforms for transistors Q2, Q3-1, and Q3-2, re-
spectively. As mentioned before, the gate drive wave-
form for transistor Q2 drives up to the battery voltage but
down only to approximately 7.5 V below the battery volt-
age. The fourth trace (in Figures 6,7) shows the voltage
at centertap of the primary winding (it is also the drain of
PMOS transistor, Q2). This waveform is essentially a
ground to a battery voltage pulse of varying duty cycle.
When the centertap of the primary is driven high, current
increases through PMOS transistor, Q2 as indicated by
the sixth trace down from the top. In region I the drain
current of Q2 is equal and opposite to the drain current of
Q3-1 since the gate of Q3-1 is high and Q3-1 is on. In
region III the drain current of Q2 will be equal and oppo-
site to the drain current of Q3-2 (not shown). In region II
when PMOS transistor Q2 is switched off, the current
through this transistor, after an initial sharp drop, ramps
back down towards zero.
In Figures 6 and 7 the fifth trace down from the top
shows the drain voltage of Q3-1. (The trace for NMOS
transistor Q3-2, not shown, would be identical, but shifted
in time by half a period.) The seventh trace down from
the top shows the current through the NMOS transistor
Q3-1, which is equal to the current in PMOS transistor
Q2 for the portion of time that PMOS transistor Q2 is
conducting (see region I, for example). As the current
ramps up in the primary winding, energy is transferred to
the secondary winding and stored in the leakage induc-
tance L_leak (and any parasitic capacitance on the second-
ary winding). If the current in the NMOS transistor is
close to zero when that NMOS transistor is turned off
that means that the CCFL circuit is being driven close to
its resonant frequency. If the circuit is being driven too
far from its resonant point then there will be large residual
currents in the transistors when they are turned off caus-
ing large ringing, lower efficiency and more stress on the
components. So called "soft switching" is achieved when
the MOS drain current is zero while the MOS is being
turned off. The driving frequency and transformer param-
eters should be chosen so that soft switching occurs.
Once PMOS transistor Q2 completes one on/off cycle,
12
it is repeated again with the alternate NMOS transistor
conducting. This complementary operation produces a
symmetric, approximately sinusoidal waveform at the in-
put to the CCFL load, as shown by the bottom trace in
Figures 6 and 7.
The operation of the CCFL circuit can be divided into 4
regions (I, II, III, and IV) as shown in Figures 6 and 7.
Figure 8-1 shows the equivalent transformer and load cir-
cuit model for region I. During region I, one of the pri-
mary windings is connected across the battery, the cur-
rent in that winding increases and energy is coupled
across to the secondary. No current flows in the other
winding because its NMOS is turned off and its body
diode is reverse biased. The drain of that NMOS stays
at twice the battery voltage because both primary wind-
ings have the same number of turns and the battery volt-
age is forced across the other primary winding.
Figure 8-2 shows the equivalent transformer and load
circuit model for region II. During region II, the battery is
disconnected from the primary winding. In this configu-
ration, current flows through both of the primary wind-
ings. The current decreases very quickly at first then
ramps down to zero at a rate that is slower than the
current ramped up. The initial drop is due to the almost
instantaneous change in inductance when current flow
shifts from one portion of the primary winding to both
portions of the primary.
Figure 8-3 shows the equivalent transformer and load
circuit model for region III. During region III, the primary
winding opposite from the one used in region I is con-
nected across the battery, increasing current in that pri-
mary winding but in a direction opposite to that of region
I. Energy is coupled across to the secondary as in re-
gion I but with opposite polarity. No current flows in the
undriven winding because its NMOS is turned off and its
body diode is reverse biased. The drain of that NMOS
stays at twice the battery voltage because both primary
windings have the same number of turns and the battery
voltage is forced on the other primary. Region III is, ef-
fectively, the inverse of region I.
Figure 8-4 shows the equivalent transformer and load
circuit model for region IV. During region IV, the battery
is disconnected from the primary winding. In this con-
figuration, current flows through both of the primary wind-
ings with opposite polarity to that in region II. The cur-
rent decreases very quickly at first then ramps down to
zero at a rate that is slower than the current ramped up.
Once again, the initial drop is due to the effective change
in inductance when current flow shifts from one portion of
the primary winding to both portions of the primary. Re-
gion IV is effectively the inverse of region II.