AK4524 Datasheet, PDF (21/31 Pages) Asahi Kasei Microsystems – 24BIT 96KHZ AUDIO CODEC

ASAHI KASEI
[AK4524]
Addr
01H
Register Name
Reset Control
RESET
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
RSTAD RSTDA
0
0
0
0
0
0
0
0
RSTDA: DAC reset
0: Reset
1: Normal Operation
The internal timing is reset by “0” and then the AOUTs go VCOM voltage immediately. The OATTs also
go “00H”. But the contents of all register are not initialized and enabled to write to the registers. After
exiting the power down mode, the OATTs fade in the setting value of the control register (06H & 07H). The
analog outputs should be muted externally as some pop noise may occur when entering to and exiting from
this mode.
RSTDA: ADC reset
0: Reset
1: Normal Operation
The internal timing is reset by “0” and then SDTO goes “L” immediately. The IPGAs also go “00H”. But
the contents of all register are not initialized and enabled to write to the register. After exiting the power
down mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, ADCs
output “0” during first 516 LRCK cycles.
Addr
02H
Register Name
Clock and Format Control
RESET
D7
DIF2
0
D6
DIF1
1
D5
DIF0
0
D4
CMODE
0
D3
CKS1
0
DFS1-0: Sampling Speed Control (see Table 2)
Initial: Normal speed
CMODE, CKS1-0: Master Clock Frequency Select (see Table 1)
Initial: 256fs
DIF2-0: Audio data interface modes (see Table 4)
000: Mode 0
001: Mode 1
010: Mode 2
011: Mode 3
100: Mode 4
Initial: 24bit MSB justified for both ADC and DAC
D2
CKS0
0
D1
DFS1
0
D0
DFS0
0
M0050-E-01
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1999/5