AK4524 Datasheet, PDF (17/31 Pages) Asahi Kasei Microsystems – 24BIT 96KHZ AUDIO CODEC

ASAHI KASEI
[AK4524]
n Power Down & Reset
The ADC and DAC of AK4524 are placed in the power-down mode by bringing a power down pin, PD “L” and each
digital filter is also reset at the same time. The internal register values are initialized by PD “L”. This reset should always
be done after power-up. And then as both control registers of ADC and DAC go reset state (RSTAD=RSTDA=”0”), each
register sholud be cancelled after doing the needed setting. In case of the ADC, an analog initialization cycle starts after
exiting the power-down or reset state. Therefore, the output data, SDTO becomes available after 516 cycles of LRCK
clock. This initialization cycle does not affect the DAC operation. Power down mode can be also controlled by the registers
(PWAD, PWDA).
Power Supply
PD pin
RSTAD(register)
RSTDA(register)
PWAD(register)
PWDA(register)
PWVR(register)
ADC Internal State
IATT
SDTO
DAC Internal State
OATT
AOUT
External Mute
Example
External clocks
in slave mode
PD Reset INITA
Normal
PD INITA
Normal
00H 00H ® XXH
XXH
00H 00H ® XXH XXH
“0”
FI
Output
“0”
FI Output
PD
Reset
Normal
PD Normal
00H
00H ® XXH
XXH
00H 00H ® XXH XXH
“0”
*
FI
*
Output
“0”
FI
*
*
MCLK, LRCK, BICK
The clocks can be stopped.
· INITA:
· PD:
· XXH:
· FI:
· AOUT:
Initializing period of ADC analog section (516/fs).
Power down state. The contents of all registers are hold.
The current value in ATT register.
Fade in. After exiting power down and reset state, ATT value fades in.
Some pop noise may occur at “*”.
Figure 7. Reset & Power down sequence
M0050-E-01
- 17 -
1999/5