AK4524 Datasheet, PDF (19/31 Pages) Asahi Kasei Microsystems – 24BIT 96KHZ AUDIO CODEC

ASAHI KASEI
[AK4524]
n Serial Control Interface
The internal registers are written by the 3 wire uP interface pins: CS, CCLK, CDTI. The data on this interface consists of
Chip address (2bits, C0/1) Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits).
Address and data is clocked in on the rising edge of CCLK. Data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CS. The operation of the control serial port may be completely asynchronous with the audio
sample rate. The maximum clock speed of the CCLK is 5MHz. The CS should be “H” or “L” if no access. The chip address
is fixed to “10”. Writing is invalid for the access to the chip address except for “10”. PD = “L” resets the registers to their
default values.
CS (CIF=1)
CS (CIF=0)
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “10”)
READ/WRITE (Fixed to “1”:WRITE)
Register Address
Control data
Figure 8. Control I/F Timing
* READ command is not supported.
n Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
Register Name
Power Down Control
Reset Control
Clock and Format Control
Deem and Volume Control
Lch IPGA Control
Rch IPGA Control
Lch ATT Control
Rch ATT Control
D7
0
0
DIF2
SMUTE
IPGL7
IPGR7
0
0
D6
0
0
DIF1
0
IPGL6
IPGR6
ATTL6
ATTR6
D5
0
0
DIF0
0
IPGL5
IPGR5
ATTL5
ATTR5
D4
0
0
CMODE
ZCEI
IPGL4
IPGR4
ATTL4
ATTR4
D3
0
0
CKS1
ZTM1
IPGL3
IPGR3
ATTL3
ATTR3
D2
PWVR
0
CKS0
ZTM0
IPGL2
IPGR2
ATTL2
ATTR2
D1
PWAD
RSTAD
DFS1
DEM1
IPGL1
IPGR1
ATTL1
ATTR1
D0
PEDA
RSTDA
DFS0
DEM0
IPGL0
IPGR0
ATTL0
ATTR0
Note: For addresses from 08H to 1FH, data is not written.
PD = “L” resets the registers to their default values.
M0050-E-01
- 19 -
1999/5