AK4366_04 Datasheet, PDF (21/31 Pages) Asahi Kasei Microsystems – Low Power 24-Bit 2ch DAC with HP-AMP

ASAHI KASEI
[AK4366]
2) Serial mode (P/S pin = “L”)
Power Supply
PDN pin
PMVCM bit
Clock Input
(1)
>150ns
(2) >0
Don’t care (3)
Don’t care
Don’t care
(9)
Don’t care
PMDAC bit
DAC Internal
State
PD
SDTI pin
DACL, DACR bit
PMHPL,
PMHPR bit
MUTEN bit
Normal Operation
(4) >0
(5) >2ms
PD
Normal Operation
PD
(4) >0
(5) >2ms
ATTL7-0
ATTR7-0 bit
HPL/R pin
00H(MUTE)
(6)
FFH(0dB)
00H(MUTE)
(8) GD (9) 1061/fs (8) (9)
(7)
(6)
FFH(0dB) 00H(MUTE)
(8) (9) (8) (9)
(7)
Figure 17. Power-up/down sequence of DAC and HP-amp
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) PMVCM and PMDAC bits should be changed to “1” after PDN pin goes to “H”.
(3) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC bit = “0”, these clocks can be
stopped. Headphone amp can operate without these clocks.
(4) DACL and DACR bits should be changed to “1” after PMDAC bit is changed to “1”.
(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2µF) after DACL and DACR bits are changed to “1”.
(6) Rise time of headphone amp is determined by external capacitor (C) of MUTET pin. The rise time up to VCOM/2 is
t_r = 100k x C(typ). When C=1µF, time constant is 100ms(typ).
(7) Fall time of headphone amp is determined by external capacitor (C) of MUTET pin. The fall time down to 0V is t_f =
200k x C(typ). When C=1µF, time constant is 200ms(typ).
PMHPL, PMHPR, DACL and DACR bits should be changed to “0” after HPL and HPR pins go to VSS.
(8) Analog output corresponding to digital input has the group delay (GD) of 20.8/fs(=472µs@fs=44.1kHz).
(9) ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
(10) Power supply should be switched off after headphone amp is powered down (HPL/R pins become “L”).
MS0248-E-01
- 21 -
2004/03