AK4366_04 Datasheet, PDF (11/31 Pages) Asahi Kasei Microsystems – Low Power 24-Bit 2ch DAC with HP-AMP

ASAHI KASEI
[AK4366]
OPERATION OVERVIEW
„ System Clock
The external clocks required to operate the AK4366 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master
clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter.
The frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency.
Table 1 shows system clock example.
LRCK
fs
8kHz
11.025kHz
12kHz
16kHz
22.05kHz
24kHz
32kHz
44.1kHz
48kHz
MCLK (MHz)
256fs
384fs
512fs
2.048
3.072
4.096
2.8224 4.2336 5.6448
3.072
4.608
6.144
4.096
6.144
8.192
5.6448 8.4672 11.2896
6.144
9.216
12.288
8.192
12.288 16.384
11.2896 16.9344 22.5792
12.288 18.432 24.576
Table 1. System Clock Example
BICK (MHz)
64fs
0.512
0.7056
0.768
1.024
1.4112
1.536
2.048
2.8224
3.072
In serial mode (P/S pin = “L”), all external clocks (MCLK, BICK and LRCK) should always be present whenever the
DAC is in normal operation mode (PMDAC bit = “1”). If these clocks are not provided, the AK4366 may draw excess
current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the
external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit = “0”). When MCLK is
input with AC coupling, the MCKAC bit should be set to “1”.
In parallel mode (P/S pin = “H”), all external clocks (MCLK, BICK and LRCK) should always be present whenever the
DAC is in normal operation mode (PDN pin = “H”). If these clocks are not provided, the AK4366 may draw excess
current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the
external clocks are not present, the DAC should be placed in power-down mode (PDN pin = “L”).
For low sampling rates, DR and S/N degrade because of the outband noise. In serial mode (P/S pin = “L”), DR and S/N
are improved by setting DFS1 bit to “1”. Table 2 shows S/N of HP-amp output. When the DFS1 bit is “1”, MCLK needs
512fs.
DFS1
0
0
1
DFS0
0
1
x
Over Sample
fs
Rate
MCLK
S/N (fs=8kHz, A-weighted)
HP-amp
64fs
8kHz∼48kHz 256fs/384fs/512fs
56dB
128fs
8kHz∼24kHz 256fs/384fs/512fs
75dB
256fs
8kHz∼12kHz
512fs
92dB
Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp
Default
MS0248-E-01
- 11 -
2004/03