AK4366_04 Datasheet, PDF (20/31 Pages) Asahi Kasei Microsystems – Low Power 24-Bit 2ch DAC with HP-AMP

ASAHI KASEI
[AK4366]
„ Power-Up/Down Sequence
1) Parallel mode (P/S pin = “H”)
(7)
Power Supply
(1)
PDN pin
>150ns
Clock Input
Don’t care (2)
Don’t care
DAC Internal
State
SDTI pin
MUTEN pin
HPL/R pin
PD
Normal Operation
PD
Normal Operation
(3) >2ms
(3) >2ms
(6) GD
(4)
(6)
(5)
(6) GD
(6)
(4)
Figure 16. Power-up/down sequence of DAC and HP-amp
PD
(5)
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PDN pin = “L”, these clocks can be
stopped. Headphone amp can operate without these clocks.
(3) MUTEN pin should be set to “H” at least 2ms after PDN pin goes to “H”.
(4) Rise time of headphone amp is determined by external capacitor (C) of MUTET pin. The rise time up to VCOM/2 is
t_r = 100k x C(typ). When C=1µF, time constant is 100ms(typ).
(5) Fall time of headphone amp is determined by external capacitor (C) of MUTET pin. The fall time down to 0V is t_f =
200k x C(typ). When C=1µF, time constant is 200ms(typ).
PDN pin should be set to “L” after HPL and HPR pins go to VSS.
(6) Analog output corresponding to digital input has the group delay (GD) of 20.8/fs (=472µs@fs=44.1kHz).
(7) Power supply should be switched off after headphone amp is powered down (HPL/R pins become “L”).
MS0248-E-01
- 20 -
2004/03