AK4425A Datasheet, PDF (18/27 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

[AK4425A]
■ Reset Function
When the MCLK, LRCK or BICK stops, the AK4425A is placed in reset mode and its analog outputs are set to VSS (0V,
typ). When the MCLK, LRCK and BICK are restarted, the AK4425A returns to normal operation mode.
Internal
State
Normal Operation
Reset
Normal Operation
D/A In
(Digital)
D/A Out
(Analog)
(1)
(3)
VSS
(3)
GD (2)
<Case1:MCLK Stop>
Clock In
MCLK, BICK, LRCK
(4) _{MCLK Stop}
<Case2:LRCK Stop>
Clock In
MCLK, BICK, LRCK
(4) _{LRCK Stop}
<Case3:BICK Stop>
Clock In
MCLK, BICK, LRCK
(4) BICK Stop
Notes:
(1) Digital data can be stopped. The click noise after MCLK, LRCK and BICK are input again can be reduced by
inputting the “0” data during this period.
(2) The analog output corresponding to a specific digital input has group delay (GD).
(3) No audible click noise occurs under normal conditions.
(4) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped).
Figure 13. Reset Timing Example
MS1127-E-01
- 18 -
2011/03