AK4425A Datasheet, PDF (12/27 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

[AK4425A]
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
-
-
-
-
-
22.5792
24.5760
MCLK (MHz)
192fs
256fs
384fs
512fs
768fs
-
-
-
16.3840 24.5760
-
-
-
22.5792 33.8688
-
-
-
24.5760 36.8640
8.192
12.288
11.2896 16.9344
12.288 18.432
-
22.5792 33.8688
-
-
-
24.5760 36.8640
-
-
33.8688
-
-
-
-
36.8640
-
-
-
-
Table 4. System Clock Example (Auto Setting Mode)
1152fs
36.8640
-
-
-
-
-
-
Sampling
Speed
Normal
Double
Quad
When MCLK= 256fs/384fs, the AK4425A supports sampling rate of 32kHz~96kHz in auto setting mode (Table 4). But,
when the sampling rate is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK=
512fs/768fs.
MCLK
256fs/384fs
512fs/768fs
DR,S/N
103dB
106dB
Table 5. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz) (Auto Setting Mode)
■ Audio Serial Interface Format
The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The DIF2-0 bit can select within five
serial data modes as shown in Table 6. In all modes the serial data is MSB-first, two’s complement format and it is latched
on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2 DIF1 DIF0
SDTI Format
BICK
0
0
0 16bit LSB Justified ≥32fs
0
0
1 20bit LSB Justified ≥40fs
0
1
0 24bit MSB Justified ≥48fs
0
1
1 24bit I²S Compatible ≥48fs
1
0
0 24bit LSB Justified ≥48fs
Table 6. Audio Data Format in Serial control mode
Figure
Figure 5
Figure 6
Figure 7
Figure 8
Figure 6
(default)
MS1127-E-01
- 12 -
2011/03