AK4642VN Datasheet, PDF (17/82 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4642]
Parameter
Symbol
min
typ
max
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
-
-
CCLK Pulse Width Low
tCCKL
80
-
-
Pulse Width High
tCCKH
80
-
-
CDTI Setup Time
tCDS
40
-
-
CDTI Hold Time
tCDH
40
-
-
CSN “H” Time
tCSW
150
-
-
CSN “↓” to CCLK “↑”
tCSS
50
-
-
CCLK “↑” to CSN “↑”
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
tCSH
50
fSCL
-
-
-
-
400
Bus Free Time Between Transmissions
tBUF
1.3
-
-
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
-
-
Clock Low Time
tLOW
1.3
-
-
Clock High Time
tHIGH
0.6
-
Setup Time for Repeated Start Condition
tSU:STA
0.6
-
-
SDA Hold Time from SCL Falling (Note 35)
tHD:DAT
0
-
-
SDA Setup Time from SCL Rising
tSU:DAT
0.1
-
-
Rise Time of Both SDA and SCL Lines
tR
-
-
0.3
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3
Setup Time for Stop Condition
tSU:STO
0.6
-
-
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
-
50
Power-down & Reset Timing
PDN Pulse Width
(Note 36)
tPD
150
-
-
PMADL or PMADR “↑” to SDTO valid (Note 37)
tPDV
-
1059
-
Note 35. σʔλ͸࠷௿300ns (SCLͷཱͪԼ͕Γ࣌ؒ)ͷؒอ࣋͞Εͳ͚Ε͹ͳΓ·ͤΜɻ
Note 36. AK4642͸PDN pin = “L”ͰϦηοτ͞Ε·͢ɻ
Note 37. PMADL bit·ͨ͸PMADR bitΛ্ཱ͔ͪ͛ͯΒͷLRCKΫϩοΫͷ “↑”ͷճ਺Ͱ͢ɻ
Units
ns
ns
ns
ns
ns
ns
ns
ns
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
1/fs
MS0358-J-02
- 17 -
2005/04