AK4642VN Datasheet, PDF (16/82 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4642]
Parameter
Symbol
min
typ
max
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
7.35
-
48
Duty
Duty
45
-
55
BICK Input Timing
Period
tBCK
1/(64fs)
-
1/(32fs)
Pulse Width Low
tBCKL
240
-
-
Pulse Width High
tBCKH
240
-
-
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
7.35
-
48
Duty
Duty
45
-
55
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
-
1/(32fs)
-
PLL3-0 bits = “0011”
tBCK
-
1/(64fs)
-
Pulse Width Low
tBCKL 0.4 x tBCK
-
-
Pulse Width High
tBCKH 0.4 x tBCK
-
-
External Slave Mode
MCKI Input Timing
Frequency 256fs
fCLK
1.8816
-
12.288
512fs
fCLK
3.7632
-
13.312
1024fs
fCLK
7.5264
-
13.312
Pulse Width Low
tCLKL 0.4/fCLK
-
-
Pulse Width High
tCLKH 0.4/fCLK
-
-
LRCK Input Timing
Frequency 256fs
fs
7.35
-
48
512fs
fs
7.35
-
26
1024fs
fs
7.35
-
13
Duty
Duty
45
-
55
BICK Input Timing
Period
tBCK
312.5
-
-
Pulse Width Low
tBCKL
130
-
-
Pulse Width High
tBCKH
130
-
-
Audio Interface Timing
Master Mode
BICK “↓” to LRCK Edge (Note 34)
tMBLR
−40
-
40
LRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
−70
-
70
BICK “↓” to SDTO
tBSD
−70
-
70
SDTI Hold Time
tSDH
50
-
-
SDTI Setup Time
tSDS
50
-
-
Slave Mode
LRCK Edge to BICK “↑” (Note 34)
tLRB
50
-
-
BICK “↑” to LRCK Edge (Note 34)
tBLR
50
-
-
LRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
-
-
80
BICK “↓” to SDTO
tBSD
-
-
80
SDTI Hold Time
tSDH
50
-
-
SDTI Setup Time
tSDS
50
-
-
Note 34. ͜ͷ֨ن஋͸LRCKͷΤοδͱBICKͷ “↑”͕ॏͳΒͳ͍Α͏ʹنఆ͍ͯ͠·͢ɻ
Units
kHz
%
ns
ns
ns
kHz
%
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MS0358-J-02
- 16 -
2005/04