AK4388 Datasheet, PDF (13/18 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit 2ch ΔΣ DAC

ASAHI KASEI
[AK4388]
SYSTEM DESIGN
Figure 7 shows the system connection diagram. An evaluation board (AKD4388) is available in order to allow an easy
study on the layout of a surrounding circuit.
Master Clock
64fs
24bit Audio Data
fs
Reset & Power down
Mode
Setting
Digital Ground
1 MCLK
DZF 16
2 BICK
DEM 15
3 SDTI
VDD 14
4 LRCK
5 RSTN
AK4388
VSS 13
VCOM 12
6 SMUTE
AOUTL 11
7 ACKS
AOUTR 10
8 DIF0
DIF1 9
Optional External
Mute Circuits
0.1u ⁺ 10u
10u
+
Analog
Supply 5V
Lch Out
Rch Out
Analog Ground
Figure 7. Typical Connection Diagram
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except DIF1 and DEM pins should not be left floating.
MS0485-E-01
- 13 -
2006/07