AK4388 Datasheet, PDF (11/18 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit 2ch ΔΣ DAC

ASAHI KASEI
[AK4388]
„ Zero Detection
When the input data at both channels are continuously zeros for 8192 LRCK cycles, DZF pin goes to “H”. DZF pin
immediately goes to “L” if input data of both channels are not zero after going DZF “H”(Figure 5).
„ Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE pin goes to “H”, the output signal is attenuated by
-∞ during 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after
starting the operation, the attenuation is discontinued and returned to 0dB by the same cycle. The soft mute is effective for
changing the signal source without stopping the signal transmission.
SMUTE bit
ATT Level
(1)
Attenuation
(1)
(3)
-∞
GD
GD
(2)
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) 1020LRCK cycles (1020/fs) at input data is attenuated to -∞.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at both channels are continuously zeros for 8192 LRCK cycles, DZF pin goes to “H”. DZF pin
immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft Mute and Zero Detection
MS0485-E-01
- 11 -
2006/07