AK5388AEQ Datasheet, PDF (10/31 Pages) Asahi Kasei Microsystems – 120dB 24-bit 192kHz 4-Channel ADC

[AK5388A]
スイッチング特性
(Ta=25°C; AVDD1/2=4.75 ∼ 5.25V; DVDD1/2=3.0 ∼ 3.6V; C_L=20pF)
Parameter
Symbol
min
Master Clock Timing
Master Clock
128fs:
fCLK
1.024
Pulse Width Low
tCLKL 0.4fCLK
Pulse Width High
tCLKH 0.4fCLK
192fs:
fCLK
1.536
Pulse Width Low
tCLKL 0.4fCLK
Pulse Width High
tCLKH 0.4fCLK
256fs:
fCLK
2.048
Pulse Width Low
tCLKL 0.4fCLK
Pulse Width High
tCLKH 0.4fCLK
384fs:
fCLK
3.072
Pulse Width Low
tCLKL 0.4fCLK
Pulse Width High
tCLKH 0.4fCLK
512fs:
fCLK
4.096
Pulse Width Low
tCLKL 0.4fCLK
Pulse Width High
tCLKH 0.4fCLK
768fs:
fCLK
6.144
Pulse Width Low
tCLKL 0.4fCLK
Pulse Width High
tCLKH 0.4fCLK
LRCK Timing (Slave Mode)
Normal mode (TDM1=“L”, TDM0=“L”)
LRCK Frequency
fs
8
Duty Cycle
Duty
45
TDM256 MODE (TDM1=“L”, TDM0=“H”)
LRCK Frequency
fs
8
“H” time
tLRH
1/256fs
“L” time
tLRL
1/256fs
TDM128 MODE (TDM1=“H”, TDM0=“H”)
LRCK Frequency
fs
8
“H” time
tLRH
1/128fs
“L” time
tLRL
1/128fs
LRCK Timing (Master Mode)
Normal mode (TDM1=“L”, TDM0=“L”)
LRCK Frequency
fs
8
Duty Cycle
Duty
TDM256 MODE (TDM1=“L”, TDM0=“H”)
LRCK Frequency
fs
8
“H” time
(Note 13) tLRH
TDM128 MODE (TDM1=“H”, TDM0=“H”)
LRCK Frequency
fs
8
“H” time
Note 13. “L” time at I²S format
(Note 13) tLRH
typ
24.576
36.864
12.288
18.432
24.576
36.864
50
1/8fs
1/4fs
max
27.648
41.472
27.648
41.472
27.648
41.472
216
55
54
216
216
54
216
Unit
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
kHz
%
kHz
ns
ns
kHz
ns
ns
kHz
%
kHz
ns
kHz
ns
MS1494-J-02
- 10 -
2013/05