CSP1027 Datasheet, PDF (50/64 Pages) Agere Systems – CSP1027 Voice Band Codec for Cellular Handset and Modem Applications

CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
Data Sheet
December 1999
9 Electrical Characteristics and Requirements (continued)
9.1 Power Dissipation
Power dissipation is highly dependent on the frequency of operation. The typical power dissipation listed is for a
selected application. The following electrical characteristics are preliminary and are subject to change.
Table 13. Power Dissipation
Operating Mode
Codec Active,
Crystal Osc. Disabled
(cioc0: ACTIVE = 1,
XOSCEN = 0,
CLK at 25 MHz,
IOCK at 6.25 MHz,
CKOS at 1 MHz)
Codec Inactive,
Crystal Osc. Disabled
(cioc0: ACTIVE = 0,
XOSCEN = 0,
CLK at 25 MHz,
IOCK at 6.25 MHz)
Codec Active,
Crystal Osc. Enabled
(cioc0: ACTIVE = 1,
XOSCEN = 1,
25 MHz crystal,
IOCK at 6.25 MHz,
CKOS at 1 MHz)
Codec Inactive,
Crystal Osc. Enabled
(cioc0: ACTIVE = 0,
XOSCEN = 1,
25 MHz crystal,
IOCK at 6.25 MHz)
Analog Supply
(VDDA)
5.0 V
Typ
Max
5.0 V
5.5 V
11.0 mA 12.2 mA
55.0 mW 67.1 mW
0.01 mA 0.02 mA
0.05 mW 0.11 mW
11.0 mA 12.2 mA
55.0 mW 67.1 mW
0.01 mA 0.02 mA
0.05 mW 0.11 mW
5.0 V
Typ
Max
5.0 V 5.5 V
4.6 mA 5.8 mA
23.0 mW 31.9 mW
3.7 mA 4.9 mA
18.5 mW 26.9 mW
10.2 mA 11.4 mA
51.0 mW 62.7 mW
9.3 mA 10.5 mA
46.5 mW 57.8 mW
Digital Supply
(VDD)
3.3 V
Typ
Max
3.3 V 3.6 V
3.0 mA 3.8 mA
9.9 mW 13.7 mW
2.5 mA 3.2 mA
8.2 mW 11.5 mW
4.1 mA 5.0 mA
13.5 mW 18.0 mW
3.6 mA 4.4 mA
11.9 mW 15.8 mW
3.0 V
Typ
Max
3.0 V 3.3 V
2.8 mA 3.5 mA
8.4 mW 11.5 mW
2.2 mA 2.9 mA
6.6 mW 9.6 mW
3.9 mA 4.7 mA
11.7 mW 15.5 mW
3.3 mA 4.1 mA
9.9 mW 13.5 mW
The power dissipation listed is for internal power dissipation only. Total power dissipation can be calculated on the
basis of the application by adding C x VDD² x f for each output, where C is the additional load capacitance and f is
the effective output frequency.
Power dissipation due to the input and I/O buffers is highly dependent on the input voltage level. At full CMOS lev-
els, essentially no dc current is drawn. However, for levels near the threshold of 0.5 x VDD, high and unstable levels
can flow. Therefore, all unused input pins should be tied inactive to VDD or VSS, and all unused I/O pins should be
tied inactive through a 10 kΩ resistor to VDD or VSS. Table 13 shows the input buffer power dissipation for inputs at
dc levels, VDD or VSS.
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Lucent Technologies Inc.