CSP1027 Datasheet, PDF (14/64 Pages) Agere Systems – CSP1027 Voice Band Codec for Cellular Handset and Modem Applications

CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
Data Sheet
December 1999
4 Architectural Information (continued)
4.3.5 Output Gains
The D/A converter output can be programmed in 3 dB
increments with the OGSEL field in the cioc0 register
(see Table 7 on page 26) to serve as a volume control.
4.3.6 Loopback Mode
The codec has a programmable loopback mode, repre-
sented by the TEST field in the cioc0 register, (see
Table 7 on page 26). As shown in Figure 3 on page 5,
when TEST = 0, the codec is in its normal mode of
operation. When TEST = 1, the loopback mode is acti-
vated. In loopback mode, the 1-bit PDM output signal
from the analog modulator is received by the analog
demodulator. At the same time, the 1-bit signal output
from the digital modulator is received by the sinc-cubic
filter in the A/D. This results in the analog input being
looped back to the analog output through the A/D and
D/A, and the digital input being looped back to the digi-
tal output through the digital filters. The loopback mode
can be useful for evaluating analog performance of the
codec in the target system without going through the
digital filters. This mode is also useful for evaluating the
response of the digital filters or in evaluating the read/
write functions of the codec and cdx registers without
having to provide an analog input to the A/D.
4.3.7 High-Pass Filter Select
The high-pass filter in the A/D and D/A can be enabled
or disabled with the HPFE field in the cioc3 register
(see Table 10 on page 29).
4.3.8 Dither
A dithering scheme is employed in the CSP1027 which
decorrelates the periodic quantization noise of the D/A
modulator to make it white noise.
∆-Σ converters are popular due to their high tolerance
to component mismatch present in integrated circuit
fabrication processes. However, ∆-Σ converters may
suffer from periodic noise and spurious tone generation
(in-band and out-of-band) due to the coarse quantiza-
tion and feedback of the ∆-Σ modulator. Although this
periodic noise may exist at very low levels (for example,
at about –90 dBm), it may be very objectionable to the
listener while having virtually no impact on the resolu-
tion of the converter. The CSP1027 D/A uses a robust
dithering scheme which eliminates any potential prob-
lems due to this phenomenon.
The DITHER field in the cioc3 register (see Table 10
on page 29) disables this feature. The default value
upon reset is DITHER = 0 (i.e., enabled). When the
DITHER is disabled, the signal-to-noise ratio will gener-
ally be about 2 dB higher. The DITHER should be
enabled if the CSP1027 is used in an audio application,
i.e., where this device interfaces to an audio trans-
ducer. If the CSP1027 is used in an application other
than audio, such as data communications, the DITHER
can be disabled if so desired.
4.4 Power-On Reset
4.4.1 Internal
The CSP1027 has a power-on reset circuit that is
ORed internally with the inversion of the reset pin,
RSTB, to form the internal reset (see Figure 16 on
page 15). The power-on reset circuit’s inverted output
is also an output pin, PORB. The PORB can be used to
provide power-on reset to the system.
The power-on reset circuit is composed of two pulse-
generating elements, its output being the OR of the
two. One element is entirely internal and generates a
power-on pulse of 1.5 ms to 7.0 ms. The second ele-
ment is composed of an input pin, PORCAP, a resistor
connected between PORCAP and VDD, and an invert-
ing input buffer. The user selects the capacitor value to
connect between PORCAP and ground that will gener-
ate a power-on pulse of desired width. The pin
PORCAP allows the user to lengthen the power-on
reset pulse to a width greater than the internal power-
on element provides. The nominal value of the resistor
is 155 kΩ, and the threshold of the inverting input buffer
is 0.6 x VDD. The formula that relates the power-on
reset pulse delay to the PORCAP capacitor is as fol-
lows:
TD = –R x C x loge (1 – 0.6)
TD = 0.9163 x R x C
Hence, to generate a 14.2 ms power-on reset pulse,
one would use a 0.1 µF capacitor connected between
PORCAP and VSS.
An internal power-on pulse can be initiated after power-
on by writing a one to the TSTPOR field in the cioc3
register (see Table 10 on page 29). This causes the
internal power-on pulse of 1.5 ms to 7.0 ms to be gen-
erated. The pulse resets the device and appears on the
PORB output pin.
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