CSP1027 Datasheet, PDF (36/64 Pages) Agere Systems – CSP1027 Voice Band Codec for Cellular Handset and Modem Applications

CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
Data Sheet
December 1999
7 Application Information (continued)
7.1.4 Microphone Regulator
VREG is a 3.0 V regulated supply that provides up to
250 µA to an external microphone or other device (see
Figure 28 on page 34). The regulator uses the external
capacitors CREG1 and CREG2 to band limit its noise
and for frequency compensation. The CREG1 off-chip
capacitor (1 µF) is required in order to meet the noise
specification of 100 µV on VREG. CREG2 (0.1 µF)
should be placed in parallel with CREG1 to improve
high-frequency noise filtering. The minimum value of
the CREG1 and CREG2 combination is 0.1 µF for VREG
to be stable. If VREG is not used, this pin should be
either connected through a 0.1 µF capacitor to analog
ground (VSSA) or tied directly to ground. Connecting
VREG to ground will produce a dc current of 250 µA to
400 µA out the VREG pin, but will not change the total
supply current. Do not leave the VREG pin unconnected
because it will oscillate.
7.2 Power Supply Configuration
Figure 28 on page 34 illustrates the recommended
configuration for the analog and digital power and
grounds.
An external supply feeds an off-chip voltage regulator.
Capacitor CD1 (10 µF) and CD2 (0.1 µF) are used for
decoupling the noise on the VDD digital power bus.
Capacitors CA1 (10 µF) and CA2 (0.1 µF) are for de-
coupling the noise on the analog power bus (VDDA).
The Ra resistor (3 Ω) decouples the analog and digital
power buses when a common 5.0 V power supply is
used. The analog and digital circuits share the same
substrate since this codec is a monolithic device. In the
technology used to fabricate the device, the substrate
is connected to ground. To avoid large substrate cur-
rents caused by digital ground-bounce, it is recom-
mended that the analog and digital grounds be tied
together at the package, as shown in Figure 28 on
page 34. It is recommended that the analog and digital
ground planes also meet at this point. In a typical appli-
cation where the CSP1027 is interfaced to a DSP, it is
advisable to place the DSP as close to the codec as
possible, with the DSP's digital ground plane extending
to the points where the SIO lines meet the CSP1027.
7.2.1 REFC Capacitor
An off-chip capacitor, CREF (0.22 µF), is required on pin
REFC in order to meet the noise requirements for the
internal signal paths.
7.2.2 Capacitor Proximity to Pins
In all cases, the external capacitors should be placed
as closely as possible to the CSP1027 pins, in order to
meet the noise specifications.
7.3 The Need for Fully Synchronous
Operation
7.3.1 Introduction to Sampled Data Systems
The analog circuits in the A/D and D/A converters are
sampled data circuits. This means that there are
switches that close to sample the signal and then open
to hold the signal. An example of this kind of discrete
time analog circuit is the well-known switched capacitor
technique used to implement A/D and D/A converter
circuits as well as filters.
A fundamental property of any sampled data system is
that any noise or signal that is in the signal path when
the sampling switches open is sampled. The sampling
process modulates the noise and signal about multi-
ples of the sample clock rate. For a sample rate of fS
and a noise tone at a frequency of fn, this modulation
process produces new tones at
(k x fS) ± fn,
where k = 1, 2, 3 . . . . For noise near a multiple of fS,
the difference term can modulate all the way down to
baseband and be heard as a tone.
A typical source of noise is that generated by the nor-
mal operation of the digital circuits. The digital circuits
tend to have fast edge transitions (large dv/dt and
di/dt). The dv/dt changes couple into the analog signal
path through parasitic capacitance on-chip and in the
circuit board. The di/dt changes cause voltages to be
generated across parasitic inductance and cause
ground-bounce on-chip. The ground-bounce can turn
on intrinsic parasitic diodes to the substrate of the
CSP1027, and the subsequent substrate currents can
couple the noise into the analog circuits. The di/dt tran-
sients are also inductively coupled into the off-chip
analog routing and thus added to the analog signals.
Layout techniques help reduce the dv/dt and di/dt cou-
pling, but it is very difficult to eliminate it.
To gauge the magnitude of the problem, consider the
numbers from the CSP1027. The digital logic swing is
ground to VDD, which can be as large as 5.5 V. The
full-scale preamplifier input level (when IRSEL = 1) is
160 mVp, and the A/D path has a noise floor that is
guaranteed to be 70 dB below full scale. For the digital
noise to raise the noise floor by less than 3 dB, the
36
Lucent Technologies Inc.