CSP1027 Datasheet, PDF (31/64 Pages) Agere Systems – CSP1027 Voice Band Codec for Cellular Handset and Modem Applications

Data Sheet
December 1999
CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
6 Signal Descriptions (continued)
6.1.5 CKO1
Clock Out 1: ICLK ÷ CDIV1 (see Table 8 on page 27).
General-purpose output clock that can be used by a
baseband codec, such as the CSP1084.
6.1.6 CKO2
Clock Out 2: CLK ÷ CDIV2 (see Table 7 on page 26).
General-purpose output clock that can be used by a
processor, such as the DSP1616.
6.2 Reset Interface
The reset interface consists of the reset input, power-
on reset input, and power-on reset output for the codec.
6.2.1 RSTB
Reset: A high-to-low transition causes entry into the
reset state. The cioc[0:3] register bits are set to their
default states.
6.2.2 PORB
Power-On Reset: A high-to-low transition indicates
entry into the power-on reset state.
6.2.3 PORCAP
Power-On Reset Capacitor: A capacitor is to be
attached to this pin for the power-on reset circuit. POR-
CAP has an internal resistor (nominal value of 155 kΩ)
connected to digital power, VDD.
6.3 Serial I/O Interface
The serial I/O interface consists of the serial clock
input, synchronizing signal, data input, data output,
serial address, and serial modes for the codec.
6.3.1 SMODE 0
Serial Mode 0: Configures the CSP1027 serial I/O
interface. When in active/passive mode (SMODE1 low),
SYNC is an output when SMODE0 is high, and SYNC
is an input when SMODE0 is low. In multiprocessor
mode (SMODE1 high), SMODE0 selects between two
possible time slots, and between two possible transmit
and receive address combinations. See Table 6 on
page 25 in the architectural information for the
addresses.
Lucent Technologies Inc.
6.3.2 SMODE1
Serial Mode 1: Configures the CSP1027 serial I/O
interface to multiprocessor mode when active-high; oth-
erwise, active/passive mode is selected when low.
6.3.3 SMODE2
Serial Mode 2: Must be tied low to configure the
CSP1027 serial I/O interface as described.
6.3.4 DI
Serial Data Input: Serial data input is latched on rising
edge of IOCK, MSB first. DI and DO should be con-
nected together when in multiprocessor mode.
6.3.5 DO
Serial Data Output: Serial data output from the output
shift register (osr), MSB first, when the data register,
cdx(A/D), is selected or codec status flag when the
control registers, cioc[0:3], are selected. When an out-
put, DO changes on the rising edges of IOCK. DI and
DO should be connected together when in multiproces-
sor mode, SMODE1 high.
6.3.6 IOCK
Serial Input/Output Clock: Input clock for serial PCM
input and output data.
Note: The frequency of the serial I/O interface clock
input IOCK (FIOCK) must be greater than the fre-
quency of the internal oversampling clock CKOS
(FCKOS).
6.3.7 SYNC
Serial Input/Output Load Strobe and Sync: When
not in multiprocessor mode, the falling edge of SYNC
indicates the beginning of a serial input and a serial
output word. The falling edge of SYNC loads the output
shift register (osr) from the codec data register
(cdx(A/D)). Sixteen IOCK clock cycles after the falling
edge of SYNC, the codec data (cdx(D/A)) or control
register (cioc) is loaded from the input shift register
(isr). SYNC is an input when the SMODE0 pin is low
and an output when the SMODE0 pin is high.
In multiprocessor mode, SYNC is the multiprocessor
synchronization input signal. A falling edge of SYNC
indicates the first word of a TDM I/O stream and
causes the resynchronization of the internal input and
output load generators.
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