CSP1027 Datasheet, PDF (24/64 Pages) Agere Systems – CSP1027 Voice Band Codec for Cellular Handset and Modem Applications

CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
Data Sheet
December 1999
4 Architectural Information (continued)
During each time slot (see Figure 26 on page 25), the
device that is assigned to that time slot drives the ADD
and DATA lines. If the assigned device's output buffer is
full, it loads its output shift register and shifts the 16 bits
of data, MSB first, out DO onto the DATA line. The 8-bit
transmit address is inverted and shifted out, LSB first,
onto the ADD line at the same time as the first 8 bits of
data. The inverted 8-bit protocol information is then
shifted out, LSB first, on the ADD line at the same time
as the last 8 bits of data. The CSP1027’s transmit
address, AT[7:0], is determined by the SMODE0 pin
(see Table 6 on page 25). The DSP’s transmit address
is determined by the srta register. The CSP1027’s pro-
tocol information is always all zeros, which is inverted
to appear as all ones on the ADD line. The DSP’s pro-
tocol information is determined by the saddx register. If
during a time slot the assigned device's output buffer is
empty, then zeros are shifted out on the DATA line and
zeros are shifted and inverted to become ones on the
ADD line.
During each time slot, each device receives the data on
the DATA line and inverts and receives the address and
protocol information on the ADD line. Each device
compares the transmitted 8-bit address with its receive
address. If the transmitted address and the device's
receive address have at least one occurrence of a one
in the same bit location, the address matches and the
device transfers the data from the input shift register to
its input buffer. If the transmitted address and the
receive address do not match, the data remains in the
input shift register and is overwritten during the next
time slot. The DSP's receive address is determined by
its srta register. Each CSP1027 has two receive
addresses, one for data and another for control, the
values of these two addresses are determined by the
SMODE0 pin (see Table 7 on page 26). When the data
receive address matches, the input shift register is
loaded into the cdx(D/A) register. When the control
receive address matches, the input shift register is
loaded into one of the four cioc registers, based upon
the two most significant bits of the 16-bit word. The
CSP1027 ignores the protocol information.
Multiprocessor communication with a CSP1027 is
intended to follow the sequence:
s The DSP writes the control registers, cioc[0:3], in the
CSP1027 to configure the clock dividers and codec.
The codec is also activated.
s The CSP1027’s A/D fills the output buffer, cdx(A/D),
and empties the input buffer, cdx(D/A), at the same
time. This causes the A/D data to be transmitted by
the CSP1027 to the DSP during the next CSP1027
time slot. The DSP’s receive address is set to match
the CSP1027’s transmit address.
s When the DSP receives A/D data from the CSP1027,
it responds by sending D/A data to the CSP1027 dur-
ing the DSP’s next time slot. The DSP’s transmit
address is set to match the CSP1027’s data receive
address. The new data is loaded into the CSP1027’s
cdx(D/A) register to be used as the next D/A sample.
s If the DSP wants to send a control word to the
CSP1027 to change the configuration or inactivate
the codec, this can be done by setting the DSP's
transmit address to match the codec's control
receive address.
Note that since the CSP1027 sends all zeros for the
protocol information, this will have to be used to identify
the A/D data from the CSP1027. If two CSP1027s are
connected to the multiprocessor bus and the DSP's
receive address is set to match both CSP1027's trans-
mit addresses, the DSP will have to identify which A/D
data came from which CSP1027 by the order in which
the data arrives, since both CSP1027s will be sending
the same protocol information.
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