TSI-1 Datasheet, PDF (5/61 Pages) Agere Systems – 1k x 1k Time-Slot Interchanger

Data Sheet, Revision 3
September 21, 2005
TSI-1
1k x 1k Time-Slot Interchanger
Figures
Table of Contents (continued)
Page
Figure 1-1. Block Diagram and High-Level Interface Definition..............................................................................................1
Figure 2-1. Package Diagram (Top View) ..............................................................................................................................7
Figure 5-1. CHICLK Timing Specifications ...........................................................................................................................19
Figure 5-2. MPUCLK Timing Specifications .........................................................................................................................19
Figure 5-3. ac Timing Specification ......................................................................................................................................20
Figure 5-4. CHI Interface Timing ..........................................................................................................................................21
Figure 5-5. Typical Receive CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK.............................................22
Figure 5-6. Transmit CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK ........................................................22
Figure 5-7. Typical Receive CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK...............................................23
Figure 5-8. Transmit CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK ..........................................................23
Figure 5-9. Typical Receive CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK...............................................24
Figure 5-10. Transmit CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK ........................................................24
Figure 5-11. Typical Receive CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK.............................................25
Figure 5-12. Transmit CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK ........................................................25
Figure 5-13. Typical Receive CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK...............................................26
Figure 5-14. Transmit CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK ..........................................................26
Figure 5-15. CHI 3-State Output Control ..............................................................................................................................27
Figure 5-16. Microprocessor Port Timing—Read Cycle .......................................................................................................28
Figure 5-17. Microprocessor Port Timing—Write Cycle .......................................................................................................29
Figure 6-1. Transmit CHI Configuration (R/W) .....................................................................................................................50
Agere Systems Inc.
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