TSI-1 Datasheet, PDF (20/61 Pages) Agere Systems – 1k x 1k Time-Slot Interchanger

TSI-1
1k x 1k Time-Slot Interchanger
Figure 5-3 shows the ac timing specifications for the CMOS outputs on the device.
80 %
80 %
20%
t9
20 %
t10
Figure 5-3. ac Timing Specification
Data Sheet, Revision 3
September 21, 2005
Table 5-3. CMOS Output ac Timing Specification *
Parameter
Description
Min
Typ
Max
Unit
t9
Rise Time (20%—80%)
—
1.5
7
ns
t10
Fall Time (80%—20%)
—
1.5
7
ns
* Test load = 50 pF (total).
20
Agere Systems Inc.