TSI-1 Datasheet, PDF (27/61 Pages) Agere Systems – 1k x 1k Time-Slot Interchanger

Data Sheet, Revision 3
September 21, 2005
TSI-1
1k x 1k Time-Slot Interchanger
CHICLK
16.384 MHz
t20
TXD
16.384 Mbits/s
CHICLK
8.192 MHz
TXD
8.192 Mbits/s
CHICLK
8.192 MHz
TXD
8.192 Mbits/s
t21
t22
Figure 5-15. CHI 3-State Output Control
Table 5-5. CHI 3-State Output Control
Control in the table below refers to bits [6:4] in Table 6-51 Transmit_CHI_Global_Configuration (Read/Write) on page 52.
This only applies if bits 13 and 12 of the corresponding register in Table 6-48 Transmit_CHI_Configuration (Read/Write) on
page 50 are set to 11.
Parameter Control
Reference Point^*
Min
Max^*
Unit
t20
000 After Previous Like Edge in 16 MHz
001 After Previous Like Edge in 16 MHz
010 After Previous Like Edge in 16 MHz
011 After Previous Like Edge in 16 MHz
t21
000 After Previous Opposite Edge in 8 MHz
001 After Previous Opposite Edge in 8 MHz
010 After Previous Opposite Edge in 8 MHz
011 After Previous Opposite Edge in 8 MHz
t22
100 After Previous Like Edge (8 MHz mode only)
101 After Previous Like Edge (8 MHz mode only)
110 After Previous Like Edge (8 MHz mode only)
111 After Previous Like Edge (8 MHz mode only)
50
59
ns
44
53
ns
38
47
ns
32
41
ns
50
59
ns
44
53
ns
38
47
ns
32
41
ns
111
120
ns
105
114
ns
99
108
ns
93
102
ns
* Like edge is the reference edge (rising or falling) as defined by bit 0 in Table 6-51 Transmit_CHI_Global_Configuration (Read/Write) on page 52.
Agere Systems Inc.
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