LU3X54FT Datasheet, PDF (43/54 Pages) Agere Systems – QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

Data Sheet
July 2000
LU3X54FT
QUAD-FET for 10Base-T/100Base-TX/FX
Timing Characteristics (Preliminary)
Table 29. MII Management Interface Timing (25 pF Load)
Name
t1
t2
t3
t4
t5
t6
Parameter
MDIO Valid to Rising Edge of MDC (setup)
Rising Edge of MDC to MDIO Invalid (hold)
MDC Falling Edge to MDIO Valid (prop. delay)
MDC High*
MDC Low*
MDC Period*
Min
Typ
10
—
10
—
0
—
—
200
40
200
80
400
Max
Unit
—
ns
—
ns
40
ns
—
ns
—
ns
—
ns
* When operating MDC above 6.25 MHz, MDC must be synchronous with LSCLK and have a setup time of 15 ns and a hold time of 5 ns,
with respect to LSCLK.
MDC
MDIO
t1
t2
Figure 10. MDIO Input Timing
MDC
MDIO
t6
t5
t4
t3
Figure 11. MDIO Output Timing
MDC
<R>
<Z>
<O>
5-4959(F).r1
5-4960(F).c
MDIO
5-5312(F)
Note: MDIO turnaround (TA) time is a 2-bit time spacing between the register address field, and the data field of a frame to avoid drive conten-
tion on MDIO during a read transaction. During a write to the LU3X54FT, these bits are driven to a 10 by the station. During a read, the
MDIO is not driven during the first bit time and is driven to a 0 by the LU3X54FT during the second bit time.
Figure 12. MDIO During TA (Turnaround) of a Read Transaction
Lucent Technologies Inc.
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