LU3X54FT Datasheet, PDF (4/54 Pages) Agere Systems – QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

LU3X54FT
QUAD-FET for 10Base-T/100Base-TX/FX
Data Sheet
July 2000
Features (continued)
100 Mbits/s FX Transceiver
s Compatible with IEEE 802.3U 100Base-FX standard
s Reuses existing twisted-pair I/O pins for compatible
fiber-optic transceiver pseudo-ECL (PECL) data:
— No additional data pins required
— Reuses existing LU3X54FT pins for fiber-optic sig-
nal detect (FOSD) inputs
s Fiber mode automatically configures port:
— Disables autonegotiation
— Disables 10Base-T
— Enables 100Base-FX remote fault signaling
— Disables MLT-3 encoder/decoder
— Disables scrambler/descrambler
s FX mode enable is pin- or register-selectable on an
individual per-port basis.
General
s Autonegotiation (IEEE 802.3u, clause 28):
— Fast link pulse (FLP) burst generator
— Arbitration function
s Bused interfaces:
— Supports either separate 10 Mbits/s and
100 Mbits/s multiport repeaters (100 Mbits/s
MII and 10 Mbits/s serial data stream), or single-
chip multispeed repeaters
— Connects ports to either the 10 Mbits/s or
100 Mbits/s buses controlled by autonegotiation
— Separate TX_EN, RX_EN, CRS, and COL pins for
each port
— Drivers on bused signal can drive up to eight
LU3X54FTs (32 ports)
s Supports the station management protocol and
frame format (clause 22):
— Basic and extended registers
— Supports next-page function
— Operates up to 12.5 MHz
— Accepts preamble suppression
— Maskable status interrupts
s Supports the following management functions via
pins if MII station management is unavailable:
— Speed select
— Carrier integrity enable
— Encoder/decoder bypass
— Scrambler/descrambler bypass
— Full duplex
— No link pulse mode
— Carrier sense select
— Autonegotiation
— 10 Mbits/s repeater reference select
— Internal 20 MHz clock synthesizer
— FX mode select
s Single 25 MHz crystal input or 25 MHz clock input,
optional 20 MHz clock input
s Supports half- and full-duplex operations
s Provides six status signals:
— Receive activity
— Transmit activity
— Full duplex
— Collision/jabber
— Link integrity
— Speed indication
s Optional LED pulse stretching
s Per-channel powerdown mode for 10 Mbits/s and
100 Mbits/s operation
s Loopback for 10 Mbits/s and 100 Mbits/s operation
s Internal pull-up or pull-down resistors to set default
powerup mode
s 0.35 µm, low-power CMOS technology
s 208-pin SQFP or 208-pin SQFPH
s Single 5 V power supply
Description
Bused MII Mode
The LU3X54FT has been designed for operation in two
basic system interface modes of operation:
s Normal MII Mode (Four Separate MII Ports). The
separate mode provides four independent RJ-45 to
MII ports and is similar to having four independent
10/100 transceivers.
s Bused MII Mode. This mode is designed specifically
for repeater applications to save pins. In bused
mode:
— Data from all of the ports operating at 100 Mbits/s
will be internally bused to system interface port A
(100 Mbits/s MII interface).
— Data from all of the ports operating at 10 Mbits/s
will be internally bused to system interface port B
(7-pin 10 Mbits/s serial interface).
The LU3X54FT will automatically detect the speed of
each port (10 Mbits/s or 100 Mbits/s) and route the
data to the appropriate port.
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Lucent Technologies Inc.