LU3X54FT Datasheet, PDF (30/54 Pages) Agere Systems – QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

LU3X54FT
QUAD-FET for 10Base-T/100Base-TX/FX
Data Sheet
July 2000
MII Station Management (continued)
Management Registers (MR)
Register Overview
The MII management 16-bit register (MR) set is implemented as described in the table below.
Table 10. MII Management Registers (MR)
Register
Address
0
1
2
3
4
5
5
6
7
8—27
28
29
30
31
Symbol
MR0
MR1
MR 2
MR 3
MR4
MR5
MR5
MR6
MR7
MR8—MR27
MR28
MR29
MR30
MR31
Name
Control Register
Status Register
PHY Identifier Register 1
PHY Identifier Register 2
Autonegotiation Advertisement Register
Autonegotiation Link Partner Ability Register
(Base Page)
Autonegotiation Link Partner Ability Register
(Next Page)
Autonegotiation Expansion Register
Next-Page Transmit Register
Reserved
Device-Specific Register 1 (Status)
Device-Specific Register 2 (100Mbits/s Control)
Device-Specific Register 3 (10Mbits/s Control)
Quick Status Register
Default
(Hex Code)
3000
7849
0180
7641
01E1
0000
—
0000
0000
0000
—
1080
0000
—
30
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