LU3X54FT Datasheet, PDF (17/54 Pages) Agere Systems – QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

Data Sheet
July 2000
LU3X54FT
QUAD-FET for 10Base-T/100Base-TX/FX
Pin Information (continued)
Pin Descriptions (continued)
Table 3. MII/Serial Interface Pins in Normal MII Mode (Four Separate MII Ports) (continued)
Pin
98
65
148
125
93, 60
143, 120
92, 59
142, 119
90, 57
140, 117
89, 56
139, 116
96
63
146
123
95
62
145
122
110
78
161
138
Signal
TX_CLK[D:A]
TXD[3:0][D:A]
Type
Description
O Transmit Clock. 25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output
in 10 Mbits/s MII mode, 10 MHz output in 10 Mbits/s serial mode. TX_CLK
provides timing reference for the transfer of the TX_EN, TXD, and TX_ER
signals sampled on the rising edge of TX_CLK.
I Transmit Data. 4-bit parallel input synchronous with TX_CLK. When
SERIAL_SEL is active-high and 10 Mbits/s mode is selected, only
TXD[0][D:A] are valid.
TX_EN[D:A]
TX_ER[D:A]/
TXD[4][D:A]
MII_EN[D:A]
I Transmit Enable. When driven high, this signal indicates there is valid data
on TXD[3:0]. TX_EN is synchronous with TX_CLK. When SERIAL_SEL is
active-high and 10 Mbits/s mode is selected, this pin indicates there is valid
data on TXD[0].
I Transmit Coding Error. When driven high, this signal causes the encoder
to intentionally corrupt the byte being transmitted across the MII (00100 will
be transmitted).
Transmit Data[4]. When the encoder/decoder bypass bit is set, this input
serves as the TXD[4] input. When in 10 Mbits/s mode and SERIAL_SEL is
active-high, this pin is ignored.
I MII Enable. For normal MII mode of operation (nonbused mode), MII_EN
for each channel must be tied high to enable each individual port being
used.
Lucent Technologies Inc.
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