TFRA08C13 Datasheet, PDF (39/188 Pages) Agere Systems – TFRA08C13 OCTAL T1/E1 Framer

Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Frame Formats (continued)
Table 11. SLC-96 Line Switch Message Codes
S1 S2 S3 S4
11 1 1
11 1 0
11 0 1
11 0 0
10 1 0
01 0 1
01 0 0
00 1 0
Code Definition
Idle
Switch line A receive
Switch line B transmit
Switch line C transmit
Switch line D transmit
Switch line B transmit and receive
Switch line B transmit and receive
Switch line B transmit and receive
Internal SLC-96 Stack Source. Optionally, a SLC-96 FDL stack may be used to insert and correspondingly extract
the FDL information in the SLC-96 frame format.
The transmit SLC-96 FDL bits are sourced from the transmit framer SLC-96 FDL stack. The SLC-96 FDL stack
(see FRM_PR31—FRM_PR35) consists of five 8-bit registers that contain the SLC-96 FS and D-bit information as
shown in Table 12. The transmit stack data is transmitted to the line when the stack enable mode is active in the
parameter registers FRM_PR21 bit 6 = 1 and FRM_PR29 bit 5—bit 7 = x10 (binary).
The receive SLC-96 stack data is received when the receive framer is in the superframe alignment state. In the
SLC-96 mode, while in the loss of superframe alignment (LSFA) state, updating of the receive framer SLC-96 stack
is halted and neither the receive stack interrupt nor receive stack flag are asserted.
Table 12. Transmit and Receive SLC-96 Stack Structure
Register Number Bit 7 (MSB)
1 (LSR)
0
2
0
3
C1
4
C9
5
M3
Bit 6
0
0
C2
C10
A1
Bit 5
0
0
C3
C11
A2
Bit 4
Bit 3
Bit 2
0
0
1
0
0
1
C4
C5
C6
SPB1 = 0 SPB2 = 1 SPB3 = 0
S1
S2
S3
Bit 1
1
1
C7
M1
S4
Bit 0 (LSB)
1
1
C8
M2
SPB4 = 1
Bit 5—bit 0 of the first 2 bytes of the SLC-96 FDL stack in Table 12 are transmitted to the line as the SLC-96 FS
sequence. Bit 7 of the third stack register is transmitted as the C1 bit of the SLC-96 D sequence. The spoiler bits
(SPB1, SPB2, SPB3, and SPB4) are taken directly from the transmit stack. The protocol for accessing the SLC-96
stack information for the transmit and receive framer is described below. The transmit SLC-96 stack must be written
with valid data when transmitting stack data.
The device indicates that it is ready for an update of its transmit stack by setting register FRM_SR4 bit 5 (SLC-96
transmit FDL stack ready) high. At this time, the system has about 9 ms to update the stack. Data written to the
stack during this interval will be transmitted during the next SLC-96 superframe D-bit interval. By reading bit 5 in
register SR4, the system clears this bit so that it can indicate the next time the transmit stack is ready. If the trans-
mit stack is not updated, then the content of the stack is retransmitted to the line. The start of the SLC-96 36-frame
FS interval of the transmit framer is a function of the first 2 bytes of the SLC-96 transmit stack registers. These
bytes must be programmed as shown in Table 12. Programming any other state into these two registers disables
the proper transmission of the SLC-96 D bits. Once programmed correctly, the transmit SLC-96 D-bit stack is trans-
mitted synchronous to the transmit SLC-96 superframe structure.
On the receive side, the device indicates that it has received data in the receive FDL stack (registers FRM_SR54—
FRM_SR58) by setting bit 4 in register FRM_SR4 (SLC-96 receive FDL stack ready) high. The system then has
about 9 ms to read the content of the stack before it is updated again (old data lost). By reading bit 4 in register
FRM_SR4, the system clears this bit so that it can indicate the next time the receive stack is ready. As explained
above, the SLC-96 receive stack is not updated when superframe alignment is lost.
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