TFRA08C13 Datasheet, PDF (128/188 Pages) Agere Systems – TFRA08C13 OCTAL T1/E1 Framer

TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet
October 2000
Framer Register Architecture (continued)
Framer Status/Counter Registers
Registers FRM_SR0—FRM_SR63 report the status of each framer. All are clear-on-read, read-only registers.
Interrupt Status Register (FRM_SR0)
The interrupt pin (INTERRUPT) goes active when a bit in this register and its associated interrupt enable bit in reg-
isters FRM_PR0—FRM_PR7 are set, and the interrupt for the framer block is enabled in register GREG1.
Table 69. Interrupt Status Register (FRM_SR0) (Y00)
Bit
Symbol
Description
0
FAC
Facility Alarm Condition. A 1 indicates a facility alarm occurred (go read FRM_SR1).
1
RAC
Remote Alarm Condition. A 1 indicates a remote alarm occurred (go read FRM_SR2).
2
FAE
Facility Alarm Event. A 1 indicates a facility alarm occurred (go read FRM_SR3 and
FRM_SR4).
3
ESE
Errored Second Event. A 1 indicates an errored second event occurred (go read
FRM_SR5, FRM_SR6, and FRM_SR7).
4
TSSFE Transmit Signaling Superframe Event. A 1 indicates that a MOS superframe block
has been transmitted and the transmit signaling data buffers are ready for new data.
5
RSSFE Receive Signaling Superframe Event. A 1 indicates that a MOS superframe block has
been received and the receive signaling data buffers must be read.
6
—
Reserved.
7
S96SR SLC-96 Stack Ready. A 1 indicates that either the transmit framer SLC-96 stack is
ready for more data or the receive framer SLC-96 stack contains new data.
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