TFRA08C13 Datasheet, PDF (118/188 Pages) Agere Systems – TFRA08C13 OCTAL T1/E1 Framer

TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet
October 2000
Reset
Both hardware and software resets are provided.
Hardware Reset (Pin C19)
Hardware reset is enabled by asserting RESET to 0. The device is in an inactive condition when RESET is 0, and
becomes active when RESET is returned to 1. Eight cycles of the LIU receive line clock, i.e., 5.2 µs for T1 or 3.9 µs
for E1, is required to guarantee a complete reset.
Hardware reset returns all framer and FDL registers to their default values, as listed in the individual register
descriptions and register maps, (Table 182—Table 186). Hardware reset results in a complete device reset includ-
ing a reset of the global registers.
Software Reset/Software Restart
Independent software reset for each functional block of the device is available. The framer may be reset through
register FRM_PR26 bit 0 (SWRESET), or placed in restart through FRM_PR26 bit 1 (SWRESTART). The FDL
receiver may be reset through register FDL_PR26 bit 1 (FRR), and the FDL transmitter may be reset through
FDL_PR1 bit 5 (FTR). The reset functions, framer SWRESET (framer software reset), FDL FRR (FDL receiver
reset), and FTR (FDL transmitter reset), reset the block and return all parameter/control registers for the block to
their default values. The restart function framer SWRESTART (framer software restart), resets the block but does
not alter the value of the parameter/control registers.
Interrupt Generation
An interrupt may be generated by any of the conditions reported in the status registers. For a bit (condition) in a sta-
tus register to create an interrupt, the corresponding interrupt enable bit must be set and the interrupt block enable
in the global register for the source block must be set, see Table 56 below. Once the source interrupt register is
read, the interrupt for that condition is deasserted.
Table 56. Status Register and Corresponding Interrupt Enable Register for Functional Blocks
Functional Block
Primary Block
Framer
Facility Data Link
Status Register
GREG0
FRM_SR0—FRM_SR7
FDL_SR0
Interrupt Enable Register
GREG1
FRM_PR0—FRM_PR7
FDL_PR2
Default for interrupt assertion is a logical 1 (high) value. But the assertion value and deasserted state is program-
mable through register GREG4 bit 4 and bit 6 and may take on the following state, see Table 57 below.
Table 57. Asserted Value and Deasserted State for GREG4 Bit 4 and Bit 6 Logic Combinations
Bit 4
0
1
0
1
Greg4
Bit 6
0
0
1
1
Interrupt (Pin AD-8)
Asserted Value
Deasserted Value
High
High
Low
Low
Low
3-state
High
3-state
Functionality
—
Wired-OR
—
Wired-AND
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