TFRA08C13 Datasheet, PDF (24/188 Pages) Agere Systems – TFRA08C13 OCTAL T1/E1 Framer

TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet
October 2000
Pin Information (continued)
Table 2. Pin Descriptions (continued)
Pins
Symbol Type*
Description
E2
N3
AA3
AC15
AB26
RFDL[1]
RFDL[2]
RFDL[3]
RFDL[4]
RFDL[5]
O Receive Facility Data Link. Serial output facility data link bit stream
extracted from the receive line data stream by the receive framer. In
DS1-DDS with data link access, this is an 8 kbits/s signal; otherwise,
4 kbits/s. In the CEPT frame format, RFDL can be programmed to one
of the RSa bits of the NOT FAS frame TS0. During loss of frame align-
ment, this signal is 1.
N23
RFDL[6]
A23
RFDL[7]
B9
RFDL[8]
D1
TCHIDATA[1] O Transmit CHI Data. Serial output system data at 2.048 Mbits/s,
P1
TCHIDATA[2]
AB1
TCHIDATA[3]
4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a high-imped-
ance state for all inactive time slots.
AF13
TCHIDATA[4]
AA25
TCHIDATA[5]
N26
TCHIDATA[6]
B22
TCHIDATA[7]
C10
TCHIDATA[8]
D3
TCHIDATAB[1] O Transmit CHI Data B. Serial output system data at 2.048 Mbits/s,
P4
TCHIDATAB[2]
AB2
TCHIDATAB[3]
4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a high-imped-
ance state for all inactive time slots.
AC12
TCHIDATAB[4]
Y23
TCHIDATAB[5]
P24
TCHIDATAB[6]
D22
TCHIDATAB[7]
A9
TCHIDATAB[8]
E1
RSSFS[1]
O Receive Framer Signaling Superframe Sync. This active-high signal
R1
RSSFS[2]
AC1
RSSFS[3]
is the CEPT signaling superframe (multiframe) synchronization pulse in
the receive framer.
AF17
RSSFS[4]
AB25
RSSFS[5]
P26
RSSFS[6]
A24
RSSFS[7]
C11
RSSFS[8]
* I^u indicates an internal pull-up, I^d indicates an internal pull-down.
† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
‡ Asserting this pin low will initially force RDY to a low state.
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