DSP16210 Datasheet, PDF (167/173 Pages) Agere Systems – DSP16210 Digital Signal Processor

Data Sheet
July 2000
DSP16210 Digital Signal Processor
Timing Characteristics and Requirements (continued)Timing Characteristics and
Requirements (continued)
Enhanced Serial I/O (continued)
VIH –
EOBC _{VIL –}
EOFS
VIH –
VIL –
EDO VOH –
VOL –
EOEB
VIH –
VIL –
t173
t174
t175
t178
t176
t178
t176
B0
B1
t182
t184
B2
B3 B14
B15
t186
t185
EOBE ^{VOH –}
t183
Figure 53. Simple Mode Output Timing Diagram
Note: Simple mode with OMODE = 1, OLEV = 0, OSIZE = 0, and OSLEV = 0.
Table 131. Timing Requirements for ESIO Simple Output Mode
Abbreviated Reference
Parameter
Min
Max
Unit
t173
EOBC Bit Clock Period (high to high)
38
—
ns
t174
EOBC Bit Clock High Time (high to low)
16
—
ns
t175
EOBC Bit Clock Low Time (low to high)
16
—
ns
t176
EOFS Hold Time (high to low or high to high)
8
—
ns
t178
EOFS Setup Time (low to high or high to high) 8
—
ns
Table 132. Timing Characteristics for ESIO Simple Output Mode
Abbreviated Reference
t182^†
t183
t184^†
t185^‡
t186^‡
Parameter
EDO Data Delay (high to valid)
EOBE Delay (low to high)
External Enable Data (low to active)
External Disable Data (high to 3-state)
EDO 3-state Delay (high to 3-state)
† EDO is active after the t182 interval or t184 interval, whichever occurs last.
‡ EDO is inactive after the t185 interval or t186 interval, whichever occurs first.
Min
Max
Unit
—
20
ns
—
20
ns
—
20
ns
—
20
ns
—
20
ns
Lucent Technologies Inc.
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