DSP16210 Datasheet, PDF (124/173 Pages) Agere Systems – DSP16210 Digital Signal Processor

DSP16210 Digital Signal Processor
Data Sheet
July 2000
Signal Descriptions (continued)
ESIO Interface (continued)
EIBC — ESIO Input Bit Clock: Input. To suit a variety
of system design requirements, EIBC can be internally
inverted (under the control of the ILEV bit of the ICR
register) to produce the internal input bit clock, IBC.
Input is at CMOS level and has typically 0.7 V hystere-
sis.
EIBF — ESIO Input Buffer Full: Positive assertion
output. When EIBF is high, the serial input buffer is full.
EDO — ESIO Data Output: Serial data (LSB-first) is
driven onto EDO on the rising edge of OBC. The rising
edge OFS indicates that the first bit of the serial output
stream is driven onto the EDO pin on the next rising
edge of OBE. EDO is programmed via OCR[5] to be
either an open-drain output driver or a 3-state output
driver. After reset, the driver is in the high-impedance
state. This signal is at CMOS level.
EOFS — ESIO Output Frame Sync: Input. EOFS
defines the beginning of a new output frame (frame
mode) or the beginning of a serial output request (sim-
ple mode). To suit a variety of system design require-
ments, EOFS can be internally inverted (under the
control of the OSLEV bit of the OCR register) to pro-
duce the internal output frame sync, OFS. Input is at
CMOS level and has typically 0.7 V hysteresis.
EOBC — ESIO Output Bit Clock: Input. To suit a vari-
ety of system design requirements, EOBC can be inter-
nally inverted (under the control of OCR register bit
OLEV) to produce the internal output bit clock, OBC.
Input is at CMOS level and has typically 0.7 V hystere-
sis.
EOEB — ESIO Data Output Enable: Negative asser-
tion input. When EOEB is high, EDO is forced into high
impedance. Input is at CMOS level and has typically
0.7 V hysteresis.
EOBE — ESIO Output Buffer Empty: Positive asser-
tion output. When EOBE is high, the serial output
buffer is empty.
SSIO Interface
The SSIO interface pins implement a full-featured
serial I/O channel.
DI — SSIO Data Input: Serial data is latched on the
rising edge of ICK, either LSB or MSB first, according
to the SSIOC register MSB field (see Table 70 on page
110).
ICK — SSIO Input Clock: Input/Output. The clock for
serial input data. In active mode, ICK is an output; in
passive mode, ICK is an input, according to the SSIOC
register ICK field (see Table 70 on page 110). Input has
typically 0.7 V hysteresis.
ILD — SSIO Input Load: Input/Output. The clock for
loading the input buffer. A falling edge of ILD indicates
the beginning of a serial input word. In active mode,
ILD is an output; in passive mode, ILD is an input,
according to the SSIOC register ILD field (see Table 70
on page 110). Input has typically 0.7 V hysteresis.
IBF — SSIO Input Buffer Full: Positive assertion out-
put. IBF is asserted when the input register, SSDX(in),
is filled. IBF is cleared when MIOU1 transfers SSDX(in)
to IORAM1. IBF is also cleared by asserting RSTB.
DO — SSIO Data Output: The serial data output either
LSB or MSB first (according to the SSIOC register
MSB field). DO normally changes on the rising edges
of OCK but can be programmed to change on falling
edges, as determined by the DODLY field of the
SSIOC register. DO is 3-stated when DOEN is high.
DOEN — SSIO Data Output Enable: Negative asser-
tion input. DO is enabled only if DOEN is low.
OCK — SSIO Output Clock: Input/Output. The clock
for serial output data. In active mode, OCK is an out-
put; in passive mode, OCK is an input, according to the
SSIOC register OCK field (see Table 70 on page 110).
Input has typically 0.7 V hysteresis.
OLD — SSIO Output Load: Input/Output. A falling
edge of OLD indicates the beginning of a serial output
word. In active mode, OLD is an output; in passive,
OLD is an input, according to the SSIOC register OLD
field (see Table 70 on page 110). Input has typically
0.7 V hysteresis.
OBE — SSIO Output Buffer Empty: Positive asser-
tion output. OBE is asserted when the output register,
SSDX(out), is emptied (moved to the output shift regis-
ter for transmission). OBE is cleared when MIOU1 fills
SSDX(out).
SYNC — SSIO Bit Counter Sync: Input. A falling
edge of SYNC causes the resynchronization of the
active ILD and OLD generators. Input has typically
0.7 V hysteresis. If unused, this pin must be pulled low
through a 10 kΩ resistor to VSS.
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