DSP16210 Datasheet, PDF (108/173 Pages) Agere Systems – DSP16210 Digital Signal Processor

DSP16210 Digital Signal Processor
Data Sheet
July 2000
Software Architecture (continued)
Registers (continued)
Register Settings (continued)
Table 68. psw1 (Processor Status Word 1) Register
15
14
13—12
Reserved IEN IPLC[1:0]
11—10
IPLP[1:0]
9—7
Reserved
6
EPAR
5—0
a[7:2]V
Bit
Field Value
Description
15 Reserved — Reserved—write with zero.
14^†
IEN^‡
0 Interrupts are globally disabled^§.
1 Interrupts are globally enabled.
13—12^† IPLC[1:0] 00 Current interrupt priority level is 0; core handles pending interrupts of priority 1, 2, or 3.
01 Current interrupt priority level is 1; core handles pending interrupts of priority 2 or 3.
10 Current interrupt priority level is 2; core handles pending interrupts of priority 3 only.
11 Current interrupt priority level is 3; core does not handle any pending interrupts^§.
11—10 IPLP[1:0] 00 Previous interrupt priority level^†† was 0.
01 Previous interrupt priority level^†† was 1.
10 Previous interrupt priority level^†† was 2.
11 Previous interrupt priority level^†† was 3.
9—7 Reserved — Reserved—write with zero.
6
EPAR 0 Most recent BMU or special function shift result has odd parity.
1 Most recent BMU or special function shift result has even parity.
5
a7V
1 a7V is set if an operation results in mathematical overflow, the result is written to a7,
and FSAT=0.
4
a6V
1 a6V is set if an operation results in mathematical overflow, the result is written to a6,
and FSAT=0.
3
a5V
1 a5V is set if an operation results in mathematical overflow, the result is written to a5,
and FSAT=0.
2
a4V
1 a4V is set if an operation results in mathematical overflow, the result is written to a4,
and FSAT=0.
1
a3V
1 a3V is set if an operation results in mathematical overflow, the result is written to a3,
and FSAT=0.
0
a2V
1 a2V is set if an operation results in mathematical overflow, the result is written to a2,
and FSAT=0.
† Cleared on reset.
‡ This bit is read only. The programmer clears this bit by executing a di instruction and sets it by executing an ei or ireturn instruction. If the
core services an interrupt, it clears this bit.
§ The core handles any pending traps.
†† Previous interrupt priority level is the priority level of the interrupt most recently serviced prior to the current interrupt. This field is used for
interrupt nesting.
108
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Lucent Technologies Inc.