DSP16210 Datasheet, PDF (139/173 Pages) Agere Systems – DSP16210 Digital Signal Processor

Data Sheet
July 2000
DSP16210 Digital Signal Processor
Timing Characteristics and Requirements (continued)
Phase-Lock Loop
Table 87. Frequency Ranges for PLL Output
Parameter
Symbol
Min
PLL Output^† Frequency Range
fPLL
50
(VDD = 3.3 V ± 0.3 V)
Input Jitter at CKI
—
—
Max
120
200
Unit
MHz
ps-rms
† The values of M and N in the pllc register (see Table 64 on page 105) must be set so that fPLL is in the
appropriate range. Choose the lowest value of N and then the appropriate value of M for
fCLK = fPLL = fCKI × M/2N.
Table 88. PLL Loop Filter Settings and Lock-In Time
M
23—24
21—22
19—20
16—18
12—15
8—11
2—7
pllc[11:8] (LF[3:0])
1011
1010
1001
1000
0111
0110
0100
Typical Lock-In Time (µs)^†
30
30
30
30
30
30
30
† Lock-in time is the time following assertion of the PLLEN bit of the pllc register
during which the PLL output clock is unstable. The DSP must operate from the
CKI input clock or from the slow ring oscillator while the PLL is locking. The
DSP16210 signals completion of the lock-in interval by setting the LOCK flag.
Lucent Technologies Inc.
DRAFT COPY
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