DSP16210 Datasheet, PDF (16/173 Pages) Agere Systems – DSP16210 Digital Signal Processor

DSP16210 Digital Signal Processor
Data Sheet
July 2000
Hardware Architecture (continued)
DSP16000 Core Architectural Overview (continued)
SYS
XAB
(20)
YAB
(20)
CACHE
31 INSTRUCTIONS
cloop (16)
cstate (16)
csave (32)
CONTROL
ins (20)
inc0 (20)
inc1 (20)
alf (16)
PSG
h (20)
i (20)
XAAU
IMMEDIATE ^{SINGLE DOUBLE}
VALUE^† –1, 0, 1 –2, 0, 2
OFF-
CORE
MUX
+
PC (20)
pt0 (20)
pt1 (20)
vbase (20)
pi (20)
pr (20)
ptrap(20)
XAB
(20)
TO
MEMORY
XAB
(20)
XDB
(32)
IDB
(32)
DAU
auc0 (16)
auc1 (16)
psw0 (16)
psw1 (16)
vsw (16)
c0 (16)
c1 (16)
c2 (16)
ar0 (16)
ar1 (16)
ar2 (16)
ar3 (16)
y (32)
SHIFT(0, –1)
SWAP MUX
x (32)
SHIFT(0, –1)
16 × 16 MULTIPLY
16 × 16 MULTIPLY
p0 (32)
SHIFT(2, 1, 0, –2)/SAT.
SHIFT(0, –1)
p1 (32)
SHIFT(2, 1, 0, –2)/SAT.
SHIFT(0, –15, –16)
DOUBLE SINGLE _IMMEDIATE
–2, 0, 2 –1, 0, 1 VALUE^‡
j (20)
k (20)
MUX
+
DEMUX
re0 (20)
re1 (20)
rb0 (20)
rb1 (20)
XDB
(32)
IDB
(32)
YAAU
FROM
MEMORY
XDB
(32)
IDB
(32)
TO
PERIPH-
ERAL
YDB
(32)
TO/FROM
MEMORY
YAB
(20)
TO
MEMORY
YAB
(20)
TRACEBACK
ENCODER
SHIFT
(0, –14)
MUX
MUX
ALU/ACS
SAT.
ADDER
SAT.
SPLIT/MUX
a0 (40)
a1 (40)
a2 (40)
a3 (40)
a4 (40)
a5 (40)
a6 (40)
a7 (40)
BMU
SAT.
COMPARE
MUX
r0 (20)
r1 (20)
r2 (20)
r3 (20)
r4 (20)
r5 (20)
r6 (20)
r7 (20)
sp (20)
KEY:
PROGRAM-ACCESSIBLE REGISTERS
MODE-CONTROLLED OPTIONS
SAT. SAT. SAT. SAT.
MUX/EXTRACT
BUSES
† Associated with PC-relative branch addressing.
‡ Associated with register-plus-displacement indirect addressing.
Figure 2. DSP16000 Core Block Diagram
16
DRAFT COPY
Lucent Technologies Inc.