CT2566 Datasheet, PDF (8/37 Pages) Aeroflex Circuit Technology – CT2566 MIL-STD-1553 to Microprocessor Interface Unit

message regardless of whether or not an error was
detected during the processing of that message.
LOOK-UP TABLES
In RTU mode a Look-Up Table is provided to allow
the CT2566 to store messages in distinct areas of RAM
based upon the subaddress of the received command
word. See RTU operation for details.
The CT2566 uses the T/R and the five subaddress
bits to form a pointer into the “current area” Look-Up
Table. The first 32 words of this table are initialized by
the user with the addresses of the data blocks to be
used for receiving data into subaddress 0,1,2,…31.
The next 32 words are initialized by the user with the
address of the data blocks to be used when
transmitting data from subaddress 0,1,2,…31.
CT2566 REGISTERS
The CT2566 is controlled through the use of three
internal registers: the Interrupt Mask Register,
Configuration Register, and Start/Reset Register. In
addition, the CT2566 can access up to four external,
user supplied registers. Possible external register
applications include: defining the RTU address, storing
a CPU Time Tag, and reading a captured Built-In-Test
(BIT) Word from the 1553 interface unit. For further
information, consult factory.
Table 2 – Internal Registers Address Definition
CT2566
Address Bits
A2 A1 A0
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
Definition
Interrupt Mask Register
Configuration Register
Not Used
Start/Reset Register (write
only)
External Register
External Register
External Register
External Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11111111
BIT
SUBSYSTEM FLAG
SERVICE REQUEST
BUSY
DB ACCEPT
STOP ON ERROR
CONTROL AREA B/A
RTU/BC/MT
Aeroflex Circuit Technology
SUBSYSTEM FLAG
SERVICE REQUEST
BUSY
DB ACCEPT
STOP ON ERROR
CONTROL AREA BIT B/A
MT
RTU/BC
DEFINITIONS
1553 status word bit.
1553 status word bit.
1553 status word bit.
1553 status word bit.
Causes BC to stop at the end of current data block if an error is detected.
Used for double buffering (See Double Buffering).
Operating Mode.
Bit 15 Bit 14 ^Mode
0
0 BC
0
1 MT
1
0 RTU
1
1 ILLEGAL
Figure 8 – Configuration Register
8
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