CT2566 Datasheet, PDF (12/37 Pages) Aeroflex Circuit Technology – CT2566 MIL-STD-1553 to Microprocessor Interface Unit

The CPU selects an internal register by asserting
MEM/REG and the A2 bit to logic "0" (See Table 2).
External registers are selected by asserting MEM/REG
logic "0" and A2 bit to a logic "1". The signals EXTEN
and EXTLD are used to read and write from the
external registers (See Figures 26 to 28).
Configuration Register
The Configuration Register is an eight bit read/write
register used to define the 1553 operating mode (BC,
MT, or RTU) and the associated RTU status bits. The
four MSBs define the mode of operation; the four LSBs
define the RTU status bits (See Figure 8).
All bits in the Configuration Register (except bit 12)
will be present on the respective CT2566 output pins to
the 1553 device. The MT bit is inverted at the output.
To begin transferring messages onto the bus, the
CPU must issue a Controller Start Command (See
Figure 14). This is done by setting bit 1 of the
Start/Reset Register to a logic "1". An EOM interrupt
will be generated each time a message transfer has
been completed. A BCEOM will be generated once the
specified number of messages has been transferred
(message counter = FFFF).
A Format Error Status Set Interrupt will be generated
at the end of a message if a timeout condition or error
condition was detected. If the STOP ON ERROR bit in
the Configuration Register is set, the CT2566 will stop
bus transactions until a new Controller Start command
is issued by the CPU. These interrupts may be masked
by the CPU through the Interrupt Mask Register.
BC START SEQUENCE
After setting the CONTROLLER START bit in the
Start/Reset Register, the CT2566 takes the following
actions:
1. Reads the Stack Pointer to get the address of the
current Descriptor Stack Entry.
2. Stores an SOM flag in the Block Status Word to
indicate a transfer operation is in progress.
3. Stores the Time Tag if used.
4. Reads the Data Block Address from the fourth
location of the Descriptor Stack and transfers the
Data Block Address into an internal Address
Register.
5. Issues a BCSTART pulse to the associated 1553
device to start the message transfers.
Note that data words are transferred to an from
memory by the associated 1553 interface unit using the
internal Address Register.
BC EOM Sequence.
Upon completion of a 1553 message (valid or invalid)
the 1553 interface unit issues an EOM pulse to the
CT2566 which takes the following actions:
1. Reads the Stack Pointer to get the address of the
current Descriptor Stack Entry.
START
ISSUE RESET COMMAND
INITIALIZE STACK POINTER
LOAD MESSAGE COUNTER
LOAD EVERY FOURTH
LOCATION OF STACK WITH
STARTING ADDRESS
LOAD MESSAGES
SET CONFIGURATION
RESISTER TO BC MODE
INITIALIZE INTERRUPT
MASK REGISTER
ISSUE START COMMAND
Figure 11
BC Initialization (under user control)
15
87
0
NOT USED
BUS CHANNEL A/B
NOT USED
MASK BROADCAST BIT
NOT USED
MODE CODE
BROADCAST
RTU TO RTU
Note: When the BC expects the BROADCAST bit set in the status
word, a logic "1" will mask the status interrupt error flag. A
FORMAT error will be generated if the MASK BROADCAST bit
is not set.
Figure 13 – BC Control Word
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