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AD9694 Datasheet, PDF (94/101 Pages) Analog Devices – 14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter
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AD9694
Data Sheet
Addr
0x0578
0x0580
0x0581
0x0583
0x0585
0x058B
Name
Bits
3
[2:0]
JESD204B [7:5]
map JTX
LMFC offset
[4:0]
JESD204B [7:0]
map JTX DID
configuration
JESD204B [7:4]
map JTX BID
configuration
[3:0]
JESD204B [7:5]
map JTX LID 0
configuration
[4:0]
JESD204B [7:5]
map JTX LID 1
configuration
[4:0]
JESD204B 7
map JTX SCR
L
configuration
[6:5]
Bit Name
Settings Description
Reset Access
1000
Transmit ILAS on ninth LMFC after SYNCINB±x
is deasserted.
1001
Transmit ILAS on 10th LMFC after SYNCINB±x is
deasserted.
1010
Transmit ILAS on 11th LMFC after SYNCINB±x is
deasserted.
1011
Transmit ILAS on 12th LMFC after SYNCINB±x is
deasserted.
1100
Transmit ILAS on 13th LMFC after SYNCINB±x is
deasserted.
1101
Transmit ILAS on 14th LMFC after SYNCINB± is
deasserted.
1110
Transmit ILAS on 15th LMFC after SYNCINB±x is
deasserted.
1111
Transmit ILAS on 16th LMFC after SYNCINB±x is
deasserted.
Reserved
Reserved.
0x0 R
Link layer test mode
0x0 R/W
000
Normal operation (link layer test mode disabled).
001
Continuous sequence of /D21.5/ characters.
010
Reserved.
011
Reserved.
100
Modified RPAT test sequence.
101
JSPAT test sequence.
110
JTSPAT test sequence.
111
Reserved.
Reserved
Reserved.
0x0 R
LMFC phase offset value
Local multiframe clock (LMFC) phase offset
value. Reset value for LMFC phase counter
when SYSREF± is asserted. Used for
deterministic delay applications.
0x0 R/W
JESD204B Tx DID value
JESD204x serial device identification (DID)
number.
0x0 R/W
Reserved
JESD204B Tx BID value
Reserved
Lane 0 LID value
Reserved
Lane 1 LID value
JESD204B scrambling
(SCR)
0
1
Reserved
Reserved.
JESD204x serial bank identification (BID)
number (extension to DID).
Reserved.
JESD204x serial lane identification (LID)
number for Lane 0.
Reserved.
JESD204x serial lane identification (LID)
number for Lane 1.
JESD204x scrambler disabled (SCR = 0).
JESD204x scrambler disabled (SCR = 1).
Reserved.
Rev. 0 | Page 94 of 101
0x0 R
0x0 R/W
0x0 R
0x0 R/W
0x0 R
0x2 R/W
0x1 R/W
0x0 R
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