AD9694 Datasheet, PDF (55/101 Pages) Analog Devices – 14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter

Data Sheet
AD9694
CONFIGURING THE JESD204B LINK
The AD9694 has two JESD204B links. The device offers an easy
way to set up the JESD204B link through the JESD04B quick
configuration register (Register 0x570). One link consists of
serial outputs SERDOUTAB0± and SERDOUTAB1± and the
second link consists of serial outputs SERDOUTCD0± and
SERDOUTCD1±). The basic parameters that determine the
link setup are
• Number of lanes per link (L)
• Number of converters per link (M)
• Number of octets per frame (F)
If the internal DDCs are used for on-chip digital processing,
M represents the number of virtual converters. The virtual
converter mapping setup is shown in Figure 91.
The maximum lane rate allowed by the JESD204B specification
is 15 Gbps. The lane line rate is related to the JESD204B
parameters using the following equation:
Lane
Line
Rate
=
M
×
N'
×
 ¹⁰
8
 ×

f_OUT
L
where:
f_OUT
=
f _{ADC _CLOCK}
Decimation Ratio
Use the following steps to configure the output:
1. Power down the link.
2. Select the quick configuration options.
3. Configure any detailed options.
4. Set the output lane mapping (optional).
5. Set additional driver configuration options (optional).
6. Power up the link.
If the lane line rate calculated is less than 6.25 Gbps, select the
low line rate option. This is done by programming a value of
0x10 to Register 0x056E.
Table 27 and Table 28 show the JESD204B output configurations
supported for both N΄ = 16 and N΄ = 8 for a given number of
virtual converters. Take care to ensure that the serial line rate
for a given configuration is within the supported range of
1.5625 Gbps to 15 Gbps.
See the Example 1: Full Bandwidth Mode section and the
Example 2: ADC with DDC Option (Two ADCs Plus Two
DDCs in Each Pair) section for two examples describing which
JESD204B transport layer settings are valid for a given chip
mode.
The decimation ratio (DCM) is the parameter programmed in
Register 0x0201.
Table 26. Virtual Converter Mapping (Per Link)
Number of Virtual
Converters Supported
1 to 2
Chip Operating Mode
(Register 0x0200, Bits[1:0])
Full bandwidth mode (0x0)
1
One DDC mode (0x1)
2
One DDC mode (0x1)
2
Two DDC mode (0x2)
4
Two DDC mode (0x2)
Chip Q Ignore
(Register 0x0200, Bit 5)
Real or complex (0x0)
Real (I only) (0x1)
Complex (I/Q) (0x0)
Real (I only) (0x1)
Complex (I/Q) (0x0)
Virtual Converter Mapping
0
1
2
ADC A/ADC C ADC B/ADC D Unused
samples
samples
DDC 0 I
samples
Unused
Unused
DDC 0 I
samples
DDC 0 Q
samples
Unused
DDC 0 I
samples
DDC 1 I
samples
Unused
DDC 0 I
samples
DDC 0 Q
samples
DDC 1 I
samples
3
Unused
Unused
Unused
Unused
DDC 1 Q
samples
Rev. 0 | Page 55 of 101