AD9694 Datasheet, PDF (89/101 Pages) Analog Devices – 14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter

Data Sheet
AD9694
Addr
0x0347
0x0550
0x0551
0x0552
0x0553
0x0554
0x0555
0x0556
Name
Pair Map
DDC 1 test
enable
Bits Bit Name
[7:3] Reserved
2
DDC 1 Q output test
mode enable
1
Reserved
0
DDC 1 I output test
mode enable
Channel map 7
test mode
control
User pattern selection
Settings Description
Reset Access
Reserved.
0x0 R
Note that Q samples always use Test Mode B/D 0x0 R/W
block.
0
Test mode disabled.
1
Test mode enabled.
Reserved.
0x0 R
Note that I samples always use Test Mode A/C 0x0 R/W
block.
0
Test mode disabled.
1
Test mode enabled.
0x0 R/W
0
Continuous repeat.
1
Single pattern.
6
Reserved
5
Reset PN long gen
4
Reset PN short gen
[3:0] Test mode selection
0
1
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
Pair map User [7:0]
Pattern1 LSB
Pair map User [7:0]
Pattern1 MSB
Pair map User [7:0]
Pattern2 LSB
Pair map User [7:0]
Pattern2 MSB
Pair map User [7:0]
Pattern3 LSB
Pair map User [7:0]
Pattern3 MSB
1111
User Pattern 1, Bits[7:0]
User Pattern 1, Bits[15:8]
User Pattern 2, Bits[7:0]
User Pattern 2, Bits[15:8]
User Pattern 3, Bits[7:0]
User Pattern 3, Bits[15:8]
Reserved.
0x0 R
0x0 R/W
Long PN enabled.
Long PN held in reset.
0x0 R/W
Short PN enabled.
Short PN held in reset.
0x0 R/W
Off—normal operation.
Midscale short.
Positive full scale.
Negative full scale.
Alternating checker board.
PN sequence—long.
PN sequence—short.
1/0 word toggle.
User pattern test mode (used with the test
mode patern selection and the User Pattern 1
through User Pattern 4 registers)
Ramp output.
User Test Pattern 1 least significant byte
0x0 R/W
User Test Pattern 1 most significant byte
0x0 R/W
User Test Pattern 2 least significant byte
0x0 R/W
User Test Pattern 2 most significant byte
0x0 R/W
User Test Pattern 3 least significant byte
0x0 R/W
User Test Pattern 3 most significant byte
0x0 R/W
Rev. 0 | Page 89 of 101