AD9694 Datasheet, PDF (1/101 Pages) Analog Devices – 14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter

Data Sheet
14-Bit, 500 MSPS JESD204B,
Quad Analog-to-Digital Converter
AD9694
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
Lane rates up to 15 Gbps
1.66 W total power at 500 MSPS
415 mW per analog-to-digital converter (ADC) channel
SFDR = 82 dBFS at 305 MHz (1.80 V p-p input range)
SNR = 66.8 dBFS at 305 MHz (1.80 V p-p input range)
Noise density = −151.5 dBFS/Hz (1.80 V p-p input range)
0.975 V, 1.8 V, and 2.5 V dc supply operation
No missing codes
Internal ADC voltage reference
Analog input buffer
On-chip dithering to improve small signal linearity
Flexible differential input range
1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)
1.4 GHz analog input full power bandwidth
Amplitude detect bits for efficient AGC implementation
4 integrated wideband digital processors
48-bit NCO, up to 4 cascaded half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
On-chip temperature diode
Flexible JESD204B lane configurations
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, W-CDMA, GSM, LTE, LTE-A
General-purpose software radios
Ultrawideband satellite receivers
Instrumentation
Radars
Signals intelligence (SIGINT)
AVDD1 AVDD1_SR
(0.975V) (0.975V)
FUNCTIONAL BLOCK DIAGRAM
AVDD2
(1.8V)
AVDD3
(2.5V)
DVDD DRVDD DRVDD2 SPIVDD
(0.975V) (0.975V) (1.8V)
(1.8V)
VIN+A
VIN–A
VCM_AB
FD_A
FD_B
VIN+B
VIN–B
BUFFER
14
ADC
CORE
FAST
DETECT
SIGNAL
MONITOR
BUFFER
14
ADC
CORE
DIGITAL DOWN
CONVERTER
(DDC)
DIGITAL DOWN
CONVERTER
(DDC)
CLK+
CLK–
VIN+C
VIN–C
VCM_CD
FD_C
FD_D
VIN+D
VIN–D
CLOCK
GENERATION
÷2
÷4
÷8
BUFFER
14
ADC
CORE
DIGITAL DOWN
CONVERTER
(DDC)
FAST
DETECT
SIGNAL
MONITOR
BUFFER
14
ADC
CORE
DIGITAL DOWN
CONVERTER
(DDC)
SPI CONTROL
JESD204B
HIGH-SPEED
SERIALIZER
2
Tx
OUTPUTS
SERDOUT0AB±
SERDOUT1AB±
SIGNAL
MONITOR
AND FAST
DETECT
JESD204B
SUBCLASS 1
CONTROL
SYSREF±
SYNCINB±AB
SYNCINB±CD
JESD204B
HIGH-SPEED
SERIALIZER
2
Tx
OUTPUTS
SERDOUT0CD±
SERDOUT1CD±
AD9694
PDWN/STBY
AGND DRGND SDIO SCLK CSB
Figure 1.
Rev. 0
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