ADSP-BF607BBCZ-5 Datasheet, PDF (93/112 Pages) Analog Devices – Blackfin Dual Core Embedded Processor

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADC Controller Module (ACM) Timing
Table 61 and Figure 48 describe ACM operations.
Note that the ACM clock (ACMx_CLK) frequency in MHz is
set by the following equation where CKDIV is a field in the
ACM_TC0 register and ranges from 1 to 255. Setup cycles (SC)
in Table 61 is also a field in the ACM_TC0 register and ranges
from 0 to 4095. Hold Cycles (HC) is a field in the ACM_TC1
register that ranges from 0 to 15.
fACLK
=
----^f--^S---^C----^L----^K----¹-----
CKDIV + 1
tACLK
=
--------¹---------
fACLK
Table 61. ACM Timing
Parameter
Timing Requirements
t_SDR
SPORT DRxPRI/DRxSEC Setup Before ACMx_CLK
t_HDR
SPORT DRxPRI/DRxSEC Hold After ACMx_CLK
Switching Characteristics
t_SCTLCS
t_HCTLCS
t_ACLKW
t_ACLK
t_HCSACLK
t_SCSACLK
ACM Controls (ACMx_A[4:0]) Setup Before Assertion of CS
ACM Control (ACMx_A[4:0]) Hold After De-assertion of CS
ACM Clock Pulse Width
ACM Clock Period¹
CS Hold to ACMx_CLK Edge
CS Setup to ACMx_CLK Edge
1 _{Whichever is greater.}
V_{DD_EXT}
1.8 V/3.3 V Nominal
Min
Max
3
1.5
(SC + 1) × t_SCLK1 – 3
HC × t_ACLK + 0.1
(t_SCLK1/2) × (CLKDIV + 1) – 1.5
[t_SCLK1 × (CKDIV + 1)] or [16]
–0.1
t_ACLK – 3.5
CS
CSPOL = 1/0
ACM_CLK
CLKPOL = 1/0
ACM
CONTROLS
DRxPRI/
DRxSEC
t_SCSACLK
t_ACLK
t_HCSACLK
t _SCTLCS
t_SDR t_HDR
t _HCTLCS
Figure 48. ACM Timing
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 93 of 112 | June 2013