ADSP-BF607BBCZ-5 Datasheet, PDF (15/112 Pages) Analog Devices – Blackfin Dual Core Embedded Processor

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
BLACKFIN
TO PLL
CIRCUITRY
ȍ
SYS_CLKIN
ȍ *
SYS_XTAL
FOR OVERTONE
OPERATION ONLY:
18 pF*
18 pF *
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
5(6,67259$/8(6+28/'%(5('8&('72ȍ
Figure 6. External Crystal Connection
The two capacitors and the series resistor shown in Figure 6 fine
tune phase and amplitude of the sine frequency. The capacitor
and resistor values shown in Figure 6 are typical values only.
The capacitor values are dependent upon the crystal manufac-
turers’ load capacitance recommendations and the PCB physical
layout. The resistor value depends on the drive level specified by
the crystal manufacturer. The user should verify the customized
values based on careful investigations on multiple devices over
temperature range.
A third-overtone crystal can be used for frequencies above 
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit as
shown in Figure 6. A design procedure for third-overtone oper-
ation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Ana-
log Devices website (www.analog.com)—use site search on 
“EE-168.”
USB Crystal Oscillator
The USB can be clocked by an external crystal, a sine wave
input, or a buffered, shaped clock derived from an external
clock oscillator. If an external clock is used, it should be a TTL
compatible signal and must not be halted, changed, or operated
below the specified frequency during normal operation. This
signal is connected to the processor’s USB_XTAL pin. Alterna-
tively, because the processor includes an on-chip oscillator
circuit, an external crystal may be used.
For fundamental frequency operation, use the circuit shown in
Figure 7. A parallel-resonant, fundamental frequency, micro-
processor grade crystal is connected between the USB_XTAL
pin and ground. A load capacitor is placed in parallel with the
crystal. The combined capacitive value of the board trace para-
sitic, the case capacitance of the crystal (from crystal
manufacturer) and the parallel capacitor in the diagram should
be in the range of 8 pF to 15 pF.
5-12 pf^{1, 2}
ȍ²
BLACKFIN
TO USB PLL
NOTES:
1. CAPACITANCE VALUE SHOWN INCLUDES BOARD PARASITICS
2. VALUES ARE A PRELIMINARY ESTIMATE.
Figure 7. External USB Crystal Connection
The crystal should be chosen so that its rated load capacitance
matches the nominal total capacitance on this node. A series
resistor may be added between the USB_XTAL pin and the par-
allel crystal and capacitor combination, in order to further
reduce the drive level of the crystal.
The parallel capacitor and the series resistor shown in Figure 7
fine tune phase and amplitude of the sine frequency. The capac-
itor and resistor values shown in Figure 7 are typical values
only. The capacitor values are dependent upon the crystal man-
ufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
Clock Generation
The clock generation unit (CGU) generates all on-chip clocks
and synchronization signals. Multiplication factors are pro-
grammed to the PLL to define the PLLCLK frequency.
Programmable values divide the PLLCLK frequency to generate
the core clock (CCLK), the system clocks (SYSCLK, SCLK0 and
SCLK1), the LPDDR or DDR2 clock (DCLK) and the output
clock (OCLK). This is illustrated in Figure 8 on Page 53.
Writing to the CGU control registers does not affect the behav-
ior of the PLL immediately. Registers are first programmed with
a new value, and the PLL logic executes the changes so that it
transitions smoothly from the current conditions to the new
ones.
SYS_CLKIN oscillations start when power is applied to the V_{DD_}
EXT ^{pins. The rising edge of SYS_HWRST can be applied after all}
voltage supplies are within specifications (see Operating Condi-
tions on Page 52), and SYS_CLKIN oscillations are stable.
Clock Out/External Clock
The SYS_CLKOUT output pin has programmable options to
output divided-down versions of the on-chip clocks. By default,
the SYS_CLKOUT pin drives a buffered version of the SYS_
CLKIN input. Clock generation faults (for example PLL unlock)
may trigger a reset by hardware. The clocks shown in Table 3
can be outputs from SYS_CLKOUT.
Rev. 0 | Page 15 of 112 | June 2013