ADSP-BF607BBCZ-5 Datasheet, PDF (60/112 Pages) Analog Devices – Blackfin Dual Core Embedded Processor

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Power-Up Reset Timing
In Figure 11, V_{DD_SUPPLIES} are V_{DD_INT}, V_{DD_EXT}, V_{DD_DMC}, V_{DD_USB},
and V_{DD_TD}.
Table 27. Power-Up Reset Timing
Parameter
Timing Requirement
t_{RST_IN_PWR} SYS_HWRST Deasserted after V_{DD_INT}, V_{DD_EXT}, V_{DD_DMC}, V_{DD_USB}, V_{DD_TD}, and SYS_
CLKIN are Stable and Within Specification
Min
11 × t_CKIN
Max
Unit
ns
RESET
CLKIN
V_{DD_SUPPLIES}
t_{RST_IN_PWR}
Figure 11. Power-Up Reset Timing
Rev. 0 | Page 60 of 112 | June 2013