EVAL-ADP1829_15 Datasheet, PDF (9/16 Pages) Analog Devices – Evaluation Board for Dual, Interleaved

PCB LAYOUT GUIDELINES
In any switching converter, some circuit paths carry high dI/dt,
which can create spikes and noise. Other circuit paths are
sensitive to noise. Still others carry high dc current and can
produce significant IR voltage drops. The key to proper PCB
layout of a switching converter is to identify these critical paths
and arrange the components and copper area accordingly.
The following is a list of recommended layout practices for
ADP1829, arranged in approximately decreasing order of
importance:
1. Keep the high current loops small. While the inductor is
considered to have continuous high current, this current is
switched alternately through the top and bottom FETs. The
current waveform in each FET is a pulse with very high
dI/dt, so the path to, through, and from each individual
FET should be as short as possible. In designs that use a
pair of D-Pak or SO-8 FETs on one side of the PCB, it is
best to counter-rotate the two so that the switch node is on
one side of the pair and the high-side drain can be
bypassed to the low-side source with a suitable ceramic
bypass capacitor, placed as close as possible to the FETs.
This minimizes inductance around this loop through the
FETs and capacitor.
In designs that place the two FETs on opposite sides of the
board, it may work well to place one FET directly opposite
to (above and below) the other to form a minimal current
loop area. Again, make sure that the high-side drain is
bypassed to the low-side source with a suitable ceramic
bypass capacitor, connected as closely as possible to the
FETs to minimize the loop area.
Recommended ceramic capacitor values range from 4.7 μF
to 22 μF depending upon the output current. This bypass
capacitor is usually connected to a larger value bulk filter
capacitor.
2. GND, IN bypass, VREG bypass, soft-start capacitors, and the
bottom ends of the output feedback divider resistors
should be tied to an (almost isolated) small ground plane
under the IC. No high current or high dI/dt signals should
be connected to this ground plane. One via should connect
GND to the die paddle heat sink area. The AGND and
PGND planes should be separated before joining them
together. Other low current signal grounds can also be
connected here if a ground connection is needed; these
EVAL-ADP1829
may include SYNC, FREQ, or LDOSD. This ground area
should be connected through one wide trace to the
negative terminal of the output filter capacitors. Because
the ADP1829 is a dual output controller, it is desirable to
place the output filters of the two output voltages adjacent
to each other. This provides the best accuracy for the two
outputs.
3. PGND pins handle high dI/dt gate drive current returning
from the source of the low-side MOSFET. The voltage at
this pin also establishes the 0 V reference for the OCP
function and the CSL pins. A small PGND plane should
connect the PGND pins and the PV bypass capacitors
through a wide and direct path to the source of the
appropriate low-side MOSFET.
4. Gate drive traces (DH and DL) handle high dI/dt so they
tend to produce noise and ringing. They should be as short
and direct as possible. If the overall PCB layout is less than
optimal, slowing down the gate drive slightly can be very
helpful to reduce noise and ringing. For this reason, it is
occasionally helpful to place small value resistors (such as
10 Ω) in series with the gate traces. These can be populated
with 0 Ω if resistance is not needed.
5. The switch node is the interconnection of the source of the
high-side FET with the drain of the low-side FET and the
inductor. This is the noisiest place in the switcher circuit
with large ac and dc voltage and current. This node should
be wide to keep resistive voltage drop down. However, to
minimize the generation of capacitively coupled noise, the
total area should be small. The best layout generally places
the FETs and inductor all close together on a small copper
plane to minimize series resistance and keep the copper
area small.
Connect a direct and moderately sized trace from the
switch node back to the SW pin and the CSL resistor. This
trace handles the high dI/dt gate current for the high-side
FET. The voltage on this trace is also sensed through the
CSL resistors and pins to sense an overcurrent condition.
The high dI/dt and sensing overcurrent do not occur at the
same time.
Keep the compensation and feedback components away
from the switch nodes and their associated components.
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