EVAL-ADP1829_15 Datasheet, PDF (4/16 Pages) Analog Devices – Evaluation Board for Dual, Interleaved

EVAL-ADP1829
MOSFET SELECTION
The choice of MOSFET directly affects the dc-to-dc converter
performance. The MOSFET must have low on resistance
(RDSON) to reduce the conduction loss, and low gate charge to
reduce switching loss.
For the low-side (synchronous) MOSFET, the dominant loss is
the conduction loss. It can be calculated as
P_C.low
=
(1
−
D)
⎜⎛
⎝
I_OUT
2₊
ΔI
2
L
12
⎟⎞
⎠
R_DSON
(7)
The gate charge loss is dissipated by the ADP1829 regulator and
gate drivers. The gate charge loss is approximated by the follow-
ing equation:
P_G = V_GQ_G f _SW
(8)
where:
VG is the driver voltage.
QG is the MOSFET total gate charge.
The high-side (main) MOSFET has to be able to handle two
main power dissipations: conduction loss and switching loss.
The switching loss is related to rise and fall times of the
MOFSET, the switching frequency, the inductor current, and
the input voltage. The high-side MOSFET switching loss is
approximated by the equation
P_T
= ^{VIN I L (t R + t F ) f SW}
2
(9)
where tR and tF are the rise and fall times of the MOSFET.
They can be calculated by
t_R
=
Q_GS
2
V_G
+ Q_GD
− V_SP
R_G
and
t_F
=
Q_GS
2
+ Q_GD
V_SP
R_G
where:
QGS and QGD are the parameters of MOSFET, provided from the
MOSFET data sheet.
RG is the resistor on the driver.
VSP is approximated using
V_SP
≈ V_TH +
I_{O UT}
g_m
where gm is the MOSFET transconductance.
The high-side MOSFET conduction loss can be calculated as
P_{C ,high}
=
D
⎜⎛
⎝
I_OUT
2
+
ΔI
2
L
12
⎟⎠⎞R_DSON
(10)
It is important to choose a high-side MOSFET that balances the
conduction loss and the switching loss.
Make sure that the selection MOSFET can meet the total power
dissipation when combining the switching and conduction loss
(generally about 1.5 W for a single D-Pak, 0.8 W for an SO-8,
and 1.2 W for a PowerPak-SO8).
SOFT START
The ADP1829 uses an adjustable soft start to limit the output
voltage ramp-up period, thus limiting the input inrush current.
The soft start is set by selecting the capacitor, CSS, from SS1 and
SS2 to GND. The ADP1829 charges CSS to 0.8 V through an
internal 90 kΩ resistor. The voltage on the soft-start capacitor
while it is charging is
V_CSS
=
0 .8
⎜⎜⎛¹
−
−
e
t _SS
RC _SS
⎟⎞
⎟
⎝
⎠
The soft start period ends when the voltage on the soft-start pin
reaches 0.6 V.
C _SS =
t _SS
−R ln ⎜⎛1 − ^0.6 ⎟⎞
⎝ 0.8 ⎠
where R = 90 kΩ and t_ss is the soft-start time.
Therefore,
C_SS = 8.015t _SS × 10 ^−6 F
(11)
CURRENT LIMIT
The ADP1829 employs a unique, programmable cycle-by-cycle
lossless current-limit circuit. In every switching cycle, the
voltage drop across the synchronous MOSFET RDSON is
measured to determine if the current is too high.
This measurement is done by an internal comparator and an
external resistor. The CSL1 and CSL2 pins are the inverting
inputs of the current-limit comparators and the noninverting
inputs are referenced to PGND1 and PGND2, respectively. A
resistor is tied between the CSL pin and the switch node, which
is the drain of the synchronous MOSFET. A 50 μA current is
forced though the resistor to set an offset voltage drop across it.
When the synchronous MOSFET is on and the voltage drop on
it exceeds the offset voltage on the external resistor, an
overcurrent fault is flagged.
When the ADP1829 senses an overcurrent condition, the next
switching cycle is suppressed, and the soft-start capacitor is
discharged. The ADP1829 remains in this mode as long as the
overcurrent condition persists. When the overcurrent condition
is removed, operation resumes in soft-start mode.
Rev. 0 | Page 4 of 16