EVAL-ADP1829_15 Datasheet, PDF (10/16 Pages) Analog Devices – Evaluation Board for Dual, Interleaved

EVAL-ADP1829
6. The negative terminal of the output filter capacitors should
be tied closely to the source of the low-side FET. Doing this
helps to minimize voltage differences between GND and
PGND at the ADP1829. The current in these capacitors is
not very high in a buck converter, but the output trace
handles the full output current of the converter. High dc
current flows through this trace to the input filter capa-
citors, so it is generally helpful to place a bulk input filter
capacitor close to the output filter capacitors on this output
ground plane. The GND connection of the ADP1829
should be connected to this output ground at the output
filter capacitors.
7. Generally, be sure that all traces are sized according to the
current to be handled as well as their sensitivity in the
circuit. Standard PCB layout guidelines mainly address
heating effects of current in a copper conductor. While
these are completely valid, they do not fully cover other
concerns such as stray inductance or dc voltage drop. Any
dc voltage differential in connections between ADP1829
GND and the converter power output ground can cause a
significant output voltage error, as it affects converter
output voltage according to the ratio with the 600 mV
feedback reference. For example, a 6 mV offset between
ground on the ADP1829 and the converter power output
causes a 1% error in the converter output voltage.
8. The CSP package has an exposed die paddle on the bottom
that efficiently conducts heat to the PCB. Adding thermal
vias to the PCB provides a thermal path to the inner or
bottom layers. Because the thermal pad is attached to the
die substrate, the planes that the thermal pad is connected
to must be electrically isolated or connected to GND.
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