EVAL-ADP1829_15 Datasheet, PDF (6/16 Pages) Analog Devices – Evaluation Board for Dual, Interleaved

EVAL-ADP1829
The compensation network consists of the error amplifier and
the impedance networks Z1 and Z2. Figure 3 shows a Type III
compensation circuit. It provides two poles and two zeros. The
transfer function of this compensator is
G_EA (s)
=
−
A_EA
s
×
⎜⎜⎝⎛^{1 +}
⎜⎜⎝⎛^{1 +}
s
2π f
Z1
⎟⎟⎠⎞
×
⎜⎜⎝⎛¹
+
s
2π f_P
1
⎟⎟⎠⎞
×
⎜⎜⎝⎛¹
+
2
2π f
Z2
⎟⎟⎠⎞
s
2π f_P2
⎟⎟⎠⎞
(14)
where:
A_EA
=
(C₁
1
+ C₂) × R₂
f _Z1
=
1
2π R₄C₂
f_Z2
=
1
2π (R₂+ R₃) × C₃
f _P1
=
1
2π R₃C₃
f_P2
=
1
2π
R₄
×
C₁C₂
C₁ + C₂
The loop gain can be written as
T(s) = ^{Gvd (s) × GEA(s)}
(15)
V_Ramp
where VRamp is the PWM ramp peak voltage; in the ADP1829,
VRamp = 1.3 V.
Use the following guidelines to select the compensation
components:
1. Set the loop gain cross frequency fC. A good choice is to
place the cross frequency fC at fs/10 for fast response.
2. Cancel ESR zero fZ by compensator pole fP1.
3. Place the high frequency pole fP2 to achieve maximum
attenuation of switching ripple and high frequency noise. A
good choice is fP2 = (5 ~ 10) fC.
4. Place two compensator zeros near the power stage resonant
frequency fO. In general, place fZ1 below fO and place fZ2
between fO and fC.
5. Check the phase margin to obtain good regulation
performance.
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