BUF04 Datasheet, PDF (9/16 Pages) Analog Devices – Closed-Loop High Speed Buffer

100
INPUT
90
(50mV/DIV)
100
INPUT
90
(2V/DIV)
BUF04
DLY 375.0ns
OUTPUT
(50mV/DIV)
10
0%
50mV
50mV
10ns
V_S = ±15V, R_L = 2kΩ, C_L = 15pF
Figure 25. Small-Signal Transient Response
OUTPUT
(2V/DIV)
10
0%
2V
2V
50ns
V_S = ±15V, R_L = 2kΩ, C_L = 15pF
Figure 26. Large-Signal Transient Response
AUDIO PRECISION BUF04 THD+N (%) vs FREQ (Hz)
0.1
07 MAR 93 21:31:53
A
0.010
VS= ±15V
LPF=80kHz
B
C
0.001
D
AA : VIN = 7.75Vrms, RL= 150W
BB ^{: VIN = 7.75Vrms, RL= 600W}
C ^{: VIN = 0.775Vrms, RL= 150W}
D ^{: VIN = 0.775Vrms, RL= 600W}
C
D
T
0.0001
20
100
1k
10k 20k
Figure 27. THD + Noise vs. Amplitude
FUNCTIONAL DESCRIPTION
The BUF04 is a closed-loop voltage buffer based on a current
feedback architecture. Its high open-loop transimpedance, high
output current drive capability, and its low input offset voltage
makes it useful in a variety of applications, such as buffering the
inputs of sampling and flash A/D converters, audio and video
line drivers, active filters, and precision op amp hoosters.
A transistor-level equivalent circuit for the BUF04 is illustrated
in Figure 29. The input stage consists of a pair of emitter
follower transistors, Q1 and Q2, whose outputs drive a second
set of transistors, Q3 and Q4. The emitters of Q3 and Q4 are
connected together through diodes, D1 and D2, to form a low
impedance input for the feedback signal (in current mode) from
the output stage. The outputs of Q3 and Q4 are then
“mirrored” to Q5 and Q6 which form the gain stage of the
BUF04. The signal is taken from the collectors of Q5 and Q6
which drive a “Darlington-connected” output stage made up of
transistors Q7-Q10. Three R-C networks (R1–C1, R2–C2, and
R3–C3) form feed-forward paths which bypass certain sections
of the BUF04 for improved high frequency performance and
capacitive load drive capability. Since the signal conveyed
internally in the BUF04 is a current, the frequency response
and slew rate of the BUF04 are insensitive to supply voltage
variations.
12
9
V_S = ±15V
T_A = +25°C
6
R_L = 150Ω
3
0
C_L = 100pF
C_L = 50pF
C_L = 0pF
–3
150 Ω
BUF04
–6
CL
10Ω
–9
–12
10k
100k
1M
10M
FREQUENCY – Hz
100M
Figure 28. Bandwidth vs. Frequency
1000M
Q11
V_IN
Q1
Q12
Q13
Q3
C1
Q5
Q7
Q9
D1
Q2
D2
R_FB
100Ω
R2
C3 _R3
20Ω
V_OUT
20Ω
Q4
C2
Q14
Q10
Q8
Q6
Figure 29. Transistor-Level Equivalent Circuit
An interesting feature of the BUF04 architecture is the use of
“slew-enhancement” transistors, Q11–Q14. Under normal small
signal (V_IN < 2 V_bes) conditions, these transistors are normally
“OFF.” In large signals, high speed transient applications where
the input signal is > 2 V_bes, these transistors turn on and literally
“brute-force” the output to follow the input. When the input
signal drops below 2 V_bes, the transistors return to their
normally “OFF” state.
REV. 0
–9–