ADSP-TS202S Datasheet, PDF (9/40 Pages) Analog Devices – TigerSHARC Embedded Processor

Preliminary Technical Data
ADSP-TS202S
the LxBCMPI input indicates that the block transfer is com-
plete. The LxDATO3–0 pins are the data output bus for the
transmitter and the LxDATI3–0 pins are the input data bus for
the receiver.
Applications can program separate error detection mechanisms
for transmit and receive operations (applications can use the
checksum mechanism to implement consecutive link port
transfers), the size of data packets, and the speed at which bytes
are transmitted.
TIMER AND GENERAL-PURPOSE I/O
The ADSP-TS202S processor has a timer pin (TMR0E) that
generates output when a programmed timer counter has
expired and four programmable general-purpose I/O pins
(FLAG3–0) that can function as either single-bit input or out-
put. As outputs, these pins can signal peripheral devices; as
inputs, they can provide the test for conditional branching.
RESET AND BOOTING
The ADSP-TS202S processor has three levels of reset:
• Power-up reset—After power-up of the system (SCLK, all
static inputs, and strap pins are stable), the RST_IN pin
must be asserted (low).
• Normal reset—For any chip reset following the power-up
reset, the RST_IN pin must be asserted (low).
• DSP-core reset—When setting the SWRST bit in
EMUCTL, the DSP core is reset, but not the external port
or I/O.
For normal operations, tie the RST_OUT pin to the POR_IN
pin.
After reset, the ADSP-TS202S processor has four boot options
for beginning operation:
• Boot from EPROM.
• Boot by an external master (host or another ADSP-TS202S
processor).
• Boot by link port.
• No boot—Start running from memory address selected
with one of the IRQ3–0 interrupt signals. See Table 2.
Using the ‘no boot’ option, the ADSP-TS202S processor must
start running from memory when one of the interrupts is
asserted.
Table 2. No Boot, Run From Memory Addresses
Interrupt
IRQ0
IRQ1
IRQ2
IRQ3
Address
0x3000 0000 (External Memory)
0x3800 0000 (External Memory)
0x8000 0000 (External Memory)
0x0000 0000 (Internal Memory)
The ADSP-TS202S processor core always exits from reset in the
idle state and waits for an interrupt. Some of the interrupts in
the interrupt vector table are initialized and enabled after reset.
For more information on boot options, see the EE-200: ADSP-
TS20xS Boot Loader Kernels Operation on the Analog Devices
website (www.analog.com)
CLOCK DOMAINS
The DSP uses calculated ratios of the SCLK clock to operate as
shown in Figure 5. The instruction execution rate is equal to
CCLK. A PLL from SCLK generates CCLK which is phase-
locked. The SCLKRATx pins define the clock multiplication of
SCLK to CCLK (see Table 4 on page 12). The link port clock is
generated from CCLK via a software programmable divisor, and
the SOC bus operates at 1/2 CCLK. Memory transfers to exter-
nal and link port buffers operate at the SOCCLK rate. SCLK also
provides clock input for the external bus interface and defines
the AC specification reference for the external bus signals. The
external bus interface runs at the SCLK frequency. The maxi-
mum SCLK frequency is one quarter the internal DSP clock
(CCLK) frequency.
EXTERNAL INTERFACE
SCLK
PLL
CCLK
(INSTRUCTION RATE)
SCLKRATx
/2
SOCCLK
(PERIPHERAL BUS RATE)
/CR
LxCLKOUT
(LINK OUTPUT RATE)
SPD BITS,
LCTLx REGISTER
Figure 5. Clock Domains
POWER DOMAINS
The ADSP-TS202S processor has separate power supply con-
nections for internal logic (V_DD), analog circuits (V_{DD_A}), I/O
buffer (V_{DD_IO}), and internal DRAM (V_{DD_DRAM}) power supply.
Note that the analog (V_{DD_A}) supply powers the clock generator
PLLs. To produce a stable clock, systems must provide a clean
power supply to power input V_{DD_A}. Designs must pay critical
attention to bypassing the V_{DD_A} supply.
FILTERING REFERENCE VOLTAGE AND CLOCKS
Figure 6 and Figure 7 show possible circuits for filtering V_REF,
and SCLK_V_REF. These circuits provide the reference voltages
for the switching voltage reference and system clock reference.
V_{DD_IO}
V_REF
R1
R2
C1
C2
V_SS
R1: 2 k⍀ SERIES RESISTOR (±1%)
R2: 2.87 k⍀ SERIES RESISTOR (±1%)
C1: 1 ␮F CAPACITOR (SMD)
C2: 1 nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS
Figure 6. V_REF Filtering Scheme
Rev. PrB | Page 9 of 40 | December 2003